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INTEGRATED CIRCUITS
DATA SHEET
SAA7140A; SAA7140B High Performance Scaler (HPS)
Objective specification Supersedes data of 1996 Jul 26 File under Integrated Circuits, IC22 1996 Sep 04
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
CONTENTS 1 2 3 4 5 6 7 7.1 7.1.1 7.1.2 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.5 7.6 7.6.1 7.7 7.7.1 7.8 7.8.1 7.8.2 7.8.3 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 9 10 11 12 13 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING (SAA7140A) PINNING (SAA7140B) FUNCTIONAL DESCRIPTION Data format/reformatter and reference signal generation Data formats and reference signals of the DMSD port Data formats and reference signals of the expansion port Acquisition control BCS control Scaling unit Horizontal prescaling Vertical scaler Horizontal variable phase scaling CSM (Colour Space Matrix), dither and gamma correction Output formatter and output FIFO register Data formats and reference signals of the VRAM port Data transfer modes Expansion port modes VRAM port modes Data burst transfer mode (FIFO Mode) Continuous data transfer mode (transparent mode) I2C-bus controlled pseudo sleep mode I2C-BUS PROTOCOL I2C-bus format I2C-bus bitmap Description of the I2C-bus bits Initial settings for the expansion and DMSD port; Subaddress 00H Initial settings for the VRAM port; subaddress 01H Port I/O control; subaddress 21H Register set A (02H to 1FH) and B (22H to 3FH) LIMITING VALUES HANDLING THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS 2 14 15 15.1 15.2 15.3 15.3.1 15.3.2 15.3.3 15.4 16 17 18
SAA7140A; SAA7140B
PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering QFP SO Method (QFP and SO) Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1996 Sep 04
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
1 FEATURES 2
SAA7140A; SAA7140B
GENERAL DESCRIPTION
* Scaling of video pictures down to randomly sized windows * Horizontal upscaling (zoom) * Two dimensional phase-correct data processing for improved signal quality of scaled data, especially for compression applications * Processing of a maximum of 2047 active samples per line (V-processing in bypass) and 2047 active lines per frame * 16-bit YUV data input port * Bidirectional expansion port with full duplex functionality (D1) or 16-bit YUV input/output * Discontinuous data stream supported * Field-wise switching between two data sources * Two independent I2C-bus programming sets * Brightness, contrast and saturation controls for scaled outputs * Chroma key ( generation) * YUV-to-RGB conversion including anti-gamma correction for RGB * 16-word FIFO register for 32-bit output data * Output configurable for 32, 24, 16 and 8-bit video data * Scaled 16-bit 4 : 2 : 2 YUV output * Scaled 15-bit RGB (5, 5, 5) + with dither and 24-bit RGB (8, 8, 8) + output * Scaled 8-bit monochrome output * Four independent user configurable general purpose I/O pins * Low power consumption in I2C-bus controlled pseudo sleep mode * Support of 5 V (SAA7140A) and pure 3.3 V (SAA7140B) signalling environment. 3 ORDERING INFORMATION TYPE NUMBER SAA7140A SAA7140B
The SAA7140A and SAA7140B are CMOS High Performance Scaler (HPS) and is a highly integrated circuit designed for use in DeskTop Video (DTV) applications. The devices resample digital video signals using two dimensional phase-correct interpolation in order to display it in an arbitrarily sized window. The SAA7140A fits perfectly into a 5 V signal environment and requires two different supply voltages (5 V and 3.3 V). The SAA7140B is a pure 3.3 V design and therefore has only 3.3 V supply pins. With respect to functions and programming, both devices are identical. The devices incorporate additional functions such as control of brightness, saturation, contrast, chroma key generation, YUV-to-RGB conversion, compensation of gamma precorrection, dithering and choice of several output formats. The SAA7140A and SAA7140B accepts data from 1 or 2 input signal sources, via it's 16-bit YUV input port and/or the bidirectional expansion port. They deliver scaled data on the 32-bit VRO output port and, if selected, also on the bidirectional expansion port. A synchronous (transparent) together with an asynchronous (burst) data transfer mode is supported at the 32-bit VRO port.
PACKAGE NAME LQFP128 LQFP128 DESCRIPTION plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm VERSION SOT425-1 SOT425-1
1996 Sep 04
3
4
ndbook, full pagewidth
EXPANSION PORT
VIDL7 to 0 LLCIO PXQIO HIO VIO FDIO
1996 Sep 04
LLCIN PXQIN HIN VIN VIDH7 to 0
VSSD(core) 1 to 4 VDDD(core) 1 to 4
Philips Semiconductors
BLOCK DIAGRAMS
1
125
126
127
105 to 112
117 to 124
128
104
103
102
97
VDDD(bord) 1 to 12 EXPANSION PORT INTERFACE
VSSD(bord) 1 to 11
SAA7140A
reference SCALING UNIT Y U V VERTICAL PROCESSING
YIN7 to 0 Y Y U V HORIZONTAL PRESCALING CONTROL LINE MEMORY ARITHMETIC HORIZONTAL FINE SCALING UV
18 to 11
DATA FORMATTER/ REFORMATTER Y
High Performance Scaler (HPS)
UVIN7 to 0
28 to 21
AND
UV
CREF ACQUISITION CONTROL BCS CONTROL
6
DMSD PORT
HREF
7
REFERENCE SIGNAL GENERATION
PXQ
VS
8
H
4
Y U V B G OUTPUT FORMATTER OUTPUT FIFO REGISTER R CSM DITHERING -CORRECTION 43 44 49 52 50 56 AP SP BTST VMUX VOEN VCLK
LLC
5
V
CLK
PORT3 to 0
38 to 41
57 to 65, 70 to 81, 86 to 96 47 46 45 48 55 54
VRO31 to 0 HGTV VSYV FLDV PXQV INCADR HFL
SCL
32
controls
SDA
31
I2C CONTROL
status
VRAM PORT
IICSA
33
RES
42
MHA117
SAA7140A; SAA7140B
Objective specification
Fig.1 Block diagram (SAA7140A).
LLCIN
PXQIN
HIN
VIN
VIDH7 to 0
handbook, full pagewidth
1996 Sep 04
EXPANSION PORT
VIDL7 to 0 LLCIO PXQIO HIO VIO FDIO 1 125 126 127 105 to 112 117 to 124 128 104 103 102 97 EXPANSION PORT INTERFACE
Philips Semiconductors
VDDD1 to 16
VSSD1 to 15
SAA7140B
reference SCALING UNIT Y U V VERTICAL PROCESSING
YIN7 to 0 Y Y U V HORIZONTAL PRESCALING CONTROL LINE MEMORY ARITHMETIC HORIZONTAL FINE SCALING UV UV
18 to 11
DATA FORMATTER/ REFORMATTER Y
High Performance Scaler (HPS)
UVIN7 to 0
28 to 21
AND
CREF PXQ H V ACQUISITION CONTROL BCS CONTROL
6
DMSD PORT
HREF
7
REFERENCE SIGNAL GENERATION
VS
8
5
Y U V B G OUTPUT FORMATTER OUTPUT FIFO REGISTER R CSM DITHERING -CORRECTION 43 44 49 52 50 56 AP SP BTST VMUX VOEN VCLK
LLC
5
CLK
PORT3 to 0
38 to 41
57 to 65, 70 to 81, 86 to 96 47 46 45 48 55 54
VRO31 to 0 HGTV VSYV FLDV PXQV INCADR HFL
SCL
32
controls
SDA
31
I2C CONTROL
status
VRAM PORT
IICSA
33
RES
42
MHA360
SAA7140A; SAA7140B
Objective specification
Fig.2 Block diagram (SAA7140B).
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
5 PINNING (SAA7140A) SYMBOL LLCIN VDDD(bord)1 VSSD(bord)1 VDDD(bord)2 LLC CREF HREF VS VDDD(core)1 VSSD(bord)2 YIN0 YIN1 YIN2 YIN3 YIN4 YIN5 YIN6 YIN7 VDDD(bord)3 VSSD(core)1 UVIN0 UVIN1 UVIN2 UVIN3 UVIN4 UVIN5 UVIN6 UVIN7 VDDD(bord)4 VSSD(bord)3 SDA SCL IICSA VDDD(bord)5 VSSD(bord)4 VDDD(bord)6 VSSD(bord)5 PORT3 PORT2 PORT1 1996 Sep 04 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I - - - I I I I - - I I I I I I I I - - I I I I I I I I - - I/O I I - - - - I/O I/O I/O
SAA7140A; SAA7140B
DESCRIPTION line-locked system clock input; expansion port digital border supply voltage 1 (+5 V) digital border ground 1 (0 V) digital border supply voltage 2 (+5 V) line-locked system clock input, maximum 32 MHz (2 x pixel rate); DMSD port clock qualifier input (HIGH indicates valid input data YUV on DMSD port) horizontal reference input signal; DMSD port vertical sync input signal; DMSD port digital core supply voltage 1 (+3.3 V) digital border ground 2 (0 V) luminance input data (bit 0); DMSD port luminance input data (bit 1); DMSD port luminance input data (bit 2); DMSD port luminance input data (bit 3); DMSD port luminance input data (bit 4); DMSD port luminance input data (bit 5); DMSD port luminance input data (bit 6); DMSD port luminance input data (bit 7); DMSD port digital border supply voltage 3 (+5 V) digital core ground 1 (0 V) time-multiplexed colour-difference input data (bit 0); DMSD port time-multiplexed colour-difference input data (bit 1); DMSD port time-multiplexed colour-difference input data (bit 2); DMSD port time-multiplexed colour-difference input data (bit 3); DMSD port time-multiplexed colour-difference input data (bit 4); DMSD port time-multiplexed colour-difference input data (bit 5); DMSD port time-multiplexed colour-difference input data (bit 6); DMSD port time-multiplexed colour-difference input data (bit 7); DMSD port digital border supply voltage 4 (+5 V) digital border ground 3 (0 V) serial data input/output (I2C-bus) serial clock input (I2C-bus) set address input (I2C-bus) digital border supply voltage 5 (+5 V) digital border ground 4 (0 V) digital border supply voltage 6 (+5 V) digital border ground 5 (0 V) general purpose port 3 input/output (set via I2C-bus) general purpose port 2 input/output (set via I2C-bus) general purpose port 1 input/output (set via I2C-bus) 6
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
SYMBOL PORT0 RES AP SP FLDV VSYV HGTV PXQV BTST VOEN VDDD(core)2 VMUX VSSD(core)2 HFL INCADR VCLK VRO31 VRO30 VRO29 VRO28 VRO27 VRO26 VRO25 VRO24 VRO23 VDDD(bord)7 VSSD(bord)6 VDDD(bord)8 VSSD(bord)7 VRO22 VRO21 VRO20 VRO19 VRO18 VRO17 VRO16 VRO15 VRO14 VRO13 VRO12 1996 Sep 04
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
I/O I/O I I I O O O O I I - I - O O I/O O O O O O O O O O - - - - O O O O O O O O O O O
DESCRIPTION general purpose port 0 input/output (set via I2C-bus) reset input (active LOW for at least 30 clock cycles) connected to ground (action pin for testing) connected to ground (shift pin for testing) field identification output signal; VRAM port vertical sync output signal; VRAM port horizontal reference output signal; VRAM port pixel qualifier output signal to mark active pixels of a qualified line; VRAM port connected to ground; BTST = HIGH sets all outputs to high-impedance state (testing) enable input signal for VRAM port digital core supply voltage 2 (+3.3 V) VRAM output multiplexing, control input for the 32 to 16-bit multiplexer digital core ground 2 (0 V) FIFO half-full flag output signal line increment/vertical reset control output clock input/output signal for VRAM port 32-bit digital VRAM port output (bit 31) 32-bit digital VRAM port output (bit 30) 32-bit digital VRAM port output (bit 29) 32-bit digital VRAM port output (bit 28) 32-bit digital VRAM port output (bit 27) 32-bit digital VRAM port output (bit 26) 32-bit digital VRAM port output (bit 25) 32-bit digital VRAM port output (bit 24) 32-bit digital VRAM port output (bit 23) digital border supply voltage 7 (+5 V) digital border ground 6 (0 V) digital border supply voltage 8 (+5 V) digital border ground 7 (0 V) 32-bit VRAM port output (bit 22) 32-bit VRAM port output (bit 21) 32-bit VRAM port output (bit 20) 32-bit VRAM port output (bit 19) 32-bit VRAM port output (bit 18) 32-bit VRAM port output (bit 17) 32-bit VRAM port output (bit 16) 32-bit VRAM port output (bit 15) 32-bit VRAM port output (bit 14) 32-bit VRAM port output (bit 13) 32-bit VRAM port output (bit 12) 7
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
SYMBOL VRO11 VSSD(bord)8 VDDD(bord)9 VSSD(core)3 VDDD(core)3 VRO10 VRO9 VRO8 VRO7 VRO6 VRO5 VRO4 VRO3 VRO2 VRO1 VRO0 FDIO VDDD(bord)10 VSSD(bord)9 VDDD(bord)11 VSSD(bord)10 VIO HIO PXQIO VIDH7 VIDH6 VIDH5 VIDH4 VIDH3 VIDH2 VIDH1 VIDH0 VDDD(bord)12
PIN 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113
I/O O - - - - O O O O O O O O O O O I/O - - - - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - 32-bit VRAM port output (bit 11) digital border ground 8 (0 V)
DESCRIPTION
digital border supply voltage 9 (+5 V) digital core ground 3 (0 V) digital core supply voltage 3 (+3.3 V) 32-bit VRAM port output (bit 10) 32-bit VRAM port output (bit 9) 32-bit VRAM port output (bit 8) 32-bit VRAM port output (bit 7) 32-bit VRAM port output (bit 6) 32-bit VRAM port output (bit 5) 32-bit VRAM port output (bit 4) 32-bit VRAM port output (bit 3) 32-bit VRAM port output (bit 2) 32-bit VRAM port output (bit 1) 32-bit VRAM port output (bit 0) field identification output signal; 7196 DIR input signal expansion port, I2C-bus controlled digital border supply voltage 10 (+5 V) digital border ground 9 (0 V) digital border supply voltage 11 (+5 V) digital border ground 10 (0 V) vertical sync input/output signal; expansion port horizontal sync input/output signal; expansion port pixel qualifier input/output signal to mark valid pixels; expansion port bidirectional expansion port, high byte (bit 7) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 6) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 5) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 4) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 3) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 2) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 1) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 0) in 16-bit mode luminance component Y digital border supply voltage 12 (+5 V)
1996 Sep 04
8
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
SYMBOL VSSD(bord)11 VDDD(core)4 VSSD(core)4 VIDL7 VIDL6 VIDL5 VIDL4 VIDL3 VIDL2 VIDL1 VIDL0 PXQIN HIN VIN LLCIO
PIN 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
I/O - - - I/O I/O I/O I/O I/O I/O I/O I/O I I I I/O digital border ground 11 (0 V)
DESCRIPTION digital core supply voltage 4 (+3.3 V) digital core ground 4 (0 V) bidirectional expansion port, low byte (bit 7) in 16-bit mode time-multiplexed colour-difference components U and V bidirectional expansion port, low byte (bit 6) in 16-bit mode time-multiplexed colour-difference components U and V bidirectional expansion port, low byte (bit 5) in 16-bit mode time-multiplexed colour-difference components U and V bidirectional expansion port, low byte (bit 4) in 16-bit mode time-multiplexed colour-difference components U and V bidirectional expansion port, low byte (bit 3) in 16-bit mode time-multiplexed colour-difference components U and V bidirectional expansion port, low byte (bit 2) in 16-bit mode time-multiplexed colour-difference components U and V bidirectional expansion port, low byte (bit 1) in 16-bit mode time-multiplexed colour-difference components U and V bidirectional expansion port, low byte (bit 0) in 16-bit mode time-multiplexed colour-difference components U and V pixel qualifier input signal to mark valid pixels; expansion port horizontal sync input signal; expansion port vertical sync input signal; expansion port line-locked system clock input/output; expansion port
1996 Sep 04
9
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
117 VIDL7 116 VSSD(core)4
handbook, full pagewidth
113 VDDD(bord)12
115 VDDD(core)4 114 VSSD(bord)11
104 PXQIO
125 PXQIN
112 VIDH0
111 VIDH1
110 VIDH2
109 VIDH3
108 VIDH4
107 VIDH5
106 VIDH6
105 VIDH7
128 LLCIO
124 VIDL0
123 VIDL1
122 VIDL2
121 VIDL3
120 VIDL4
119 VIDL5
118 VIDL6
LLCIN VDDD(bord)1 VSSD(bord)1 VDDD(bord)2 LCC CREF HREF VS VDDD(core)1 VSSD(bord)2 YIN0 YIN1 YIN2 YIN3 YIN4 YIN5 YIN6 YIN7 VDDD(bord)3 VSSD(core)1 UVIN0 UVIN1 UVIN2 UVIN3 UVIN4 UVIN5 UVIN6 UVIN7 VDDD(bord)4 VSSD(bord)3 SDA SCL IICSA VDDD(bord)5 VSSD(bord)4 VDDD(bord)6 VSSD(bord)5 PORT3
103 HIO 102 VIO 101 VSSD(bord)10 100 VDDD(bord)11 99 VSSD(bord)9 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VDDD(bord)10 FDIO VRO0 VRO1 VRO2 VRO3 VRO4 VRO5 VRO5 VRO7 VRO8 VRO9 VRO10 VDDD(core)3 VSSD(core)3 VDDD(bord)9 VSSD(bord)8 VRO11 VRO12 VRO13 VRO14 VRO15 VRO16 VRO17 VRO18 VRO19 VRO20 VRO21 VRO22 VSSD(bord)7 VDDD(bord)8 VSSD(bord)6 VDDD(bord)7 VRO23 64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
126 HIN
127 VIN
SAA7140A
MHA362
VDDD(core)2
VMUX VSSD(core)2
RES
VSYV
HGTV
AP
SP
FLDV
PXQV
BTST
VOEN
HFL
INCADR
VCLK
VRO31
VRO30
VRO29
VRO28
VRO27
VRO26
VRO25
PORT2
PORT1
PORT0
Fig.3 Pin configuration (SAA7140A).
1996 Sep 04
10
VRO24
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
6 PINNING (SAA7140B) SYMBOL LLCIN VDDD1 VSSD1 VDDD2 LLC CREF HREF VS VDDD3 VSSD2 YIN0 YIN1 YIN2 YIN3 YIN4 YIN5 YIN6 YIN7 VDDD4 VSSD3 UVIN0 UVIN1 UVIN2 UVIN3 UVIN4 UVIN5 UVIN6 UVIN7 VDDD5 VSSD4 SDA SCL IICSA VDDD6 VSSD5 VDDD7 VSSD6 PORT3 PORT2 PORT1 1996 Sep 04 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I - - - I I I I - - I I I I I I I I - - I I I I I I I I - - I/O I I - - - - I/O I/O I/O digital supply voltage 1 (+3.3 V) digital ground 1 (0 V) digital supply voltage 2 (+3.3 V)
SAA7140A; SAA7140B
DESCRIPTION line-locked system clock input; expansion port
line-locked system clock input, maximum 32 MHz (2 x pixel rate); DMSD port clock qualifier input (HIGH indicates valid input data YUV on DMSD port) horizontal reference input signal; DMSD port vertical sync input signal; DMSD port digital supply voltage 3 (+3.3 V) digital ground 2 (0 V) luminance input data (bit 0); DMSD port luminance input data (bit 1); DMSD port luminance input data (bit 2); DMSD port luminance input data (bit 3); DMSD port luminance input data (bit 4); DMSD port luminance input data (bit 5); DMSD port luminance input data (bit 6); DMSD port luminance input data (bit 7); DMSD port digital supply voltage 4 (+3.3 V) digital ground 3 (0 V) time-multiplexed colour-difference input data (bit 0); DMSD port time-multiplexed colour-difference input data (bit 1); DMSD port time-multiplexed colour-difference input data (bit 2); DMSD port time-multiplexed colour-difference input data (bit 3); DMSD port time-multiplexed colour-difference input data (bit 4); DMSD port time-multiplexed colour-difference input data (bit 5); DMSD port time-multiplexed colour-difference input data (bit 6); DMSD port time-multiplexed colour-difference input data (bit 7); DMSD port digital supply voltage 5 (+3.3 V) digital ground 4 (0 V) serial data input/output (I2C-bus) serial clock input (I2C-bus) set address input (I2C-bus) digital supply voltage 6 (+3.3 V) digital ground 5 (0 V) digital supply voltage 7 (+3.3 V) digital ground 6 (0 V) general purpose port 3 input/output (set via I2C-bus) general purpose port 2 input/output (set via I2C-bus) general purpose port 1 input/output (set via I2C-bus) 11
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
SYMBOL PORT0 RES AP SP FLDV VSYV HGTV PXQV BTST VOEN VDDD8 VMUX VSSD7 HFL INCADR VCLK VRO31 VRO30 VRO29 VRO28 VRO27 VRO26 VRO25 VRO24 VRO23 VDDD9 VSSD8 VDDD10 VSSD9 VRO22 VRO21 VRO20 VRO19 VRO18 VRO17 VRO16 VRO15 VRO14 VRO13 VRO12 1996 Sep 04
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
I/O I/O I I I O O O O I I - I - O O I/O O O O O O O O O O - - - - O O O O O O O O O O O
DESCRIPTION general purpose port 0 input/output (set via I2C-bus) reset input (active LOW for at least 30 clock cycles) connected to ground (action pin for testing) connected to ground (shift pin for testing) field identification output signal; VRAM port vertical sync output signal; VRAM port horizontal reference output signal; VRAM port pixel qualifier output signal to mark active pixels of a qualified line; VRAM port connected to ground; BTST = HIGH sets all outputs to high-impedance state (testing) enable input signal for VRAM port digital supply voltage 8 (+3.3 V) VRAM output multiplexing, control input for the 32 to 16-bit multiplexer digital ground 7 (0 V) FIFO half-full flag output signal line increment/vertical reset control output clock input/output signal for VRAM port 32-bit digital VRAM port output (bit 31) 32-bit digital VRAM port output (bit 30) 32-bit digital VRAM port output (bit 29) 32-bit digital VRAM port output (bit 28) 32-bit digital VRAM port output (bit 27) 32-bit digital VRAM port output (bit 26) 32-bit digital VRAM port output (bit 25) 32-bit digital VRAM port output (bit 24) 32-bit digital VRAM port output (bit 23) digital supply voltage 9 (+3.3 V) digital ground 8 (0 V) digital supply voltage 10 (+3.3 V) digital ground 9 (0 V) 32-bit VRAM port output (bit 22) 32-bit VRAM port output (bit 21) 32-bit VRAM port output (bit 20) 32-bit VRAM port output (bit 19) 32-bit VRAM port output (bit 18) 32-bit VRAM port output (bit 17) 32-bit VRAM port output (bit 16) 32-bit VRAM port output (bit 15) 32-bit VRAM port output (bit 14) 32-bit VRAM port output (bit 13) 32-bit VRAM port output (bit 12) 12
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
SYMBOL VRO11 VSSD10 VDDD11 VSSD11 VDDD12 VRO10 VRO9 VRO8 VRO7 VRO6 VRO5 VRO4 VRO3 VRO2 VRO1 VRO0 FDIO VDDD13 VSSD12 VDDD14 VSSD13 VIO HIO PXQIO VIDH7 VIDH6 VIDH5 VIDH4 VIDH3 VIDH2 VIDH1 VIDH0 VDDD15
PIN 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113
I/O O - - - - O O O O O O O O O O O I/O - - - - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - 32-bit VRAM port output (bit 11) digital ground 10 (0 V) digital supply voltage 11 (+3.3 V) digital ground 11 (0 V) digital supply voltage 12 (+3.3 V) 32-bit VRAM port output (bit 10) 32-bit VRAM port output (bit 9) 32-bit VRAM port output (bit 8) 32-bit VRAM port output (bit 7) 32-bit VRAM port output (bit 6) 32-bit VRAM port output (bit 5) 32-bit VRAM port output (bit 4) 32-bit VRAM port output (bit 3) 32-bit VRAM port output (bit 2) 32-bit VRAM port output (bit 1) 32-bit VRAM port output (bit 0)
DESCRIPTION
field identification output signal; 7196 DIR input signal expansion port, I2C-bus controlled digital supply voltage 13 (+3.3 V) digital ground 12 (0 V) digital supply voltage 14 (+3.3 V) digital ground 13 (0 V) vertical sync input/output signal; expansion port horizontal sync input/output signal; expansion port pixel qualifier input/output signal to mark valid pixels; expansion port bidirectional expansion port, high byte (bit 7) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 6) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 5) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 4) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 3) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 2) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 1) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 0) in 16-bit mode luminance component Y digital supply voltage 15 (+3.3 V)
1996 Sep 04
13
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
SYMBOL VSSD14 VDDD16 VSSD15 VIDL7 VIDL6 VIDL5 VIDL4 VIDL3 VIDL2 VIDL1 VIDL0 PXQIN HIN VIN LLCIO
PIN 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
I/O - - - I/O I/O I/O I/O I/O I/O I/O I/O I I I I/O digital ground 14 (0 V) digital supply voltage 16 (+3.3 V) digital ground 15 (0 V)
DESCRIPTION
bidirectional expansion port, low byte (bit 7) in 16-bit mode time-multiplexed colour-difference components U and V bidirectional expansion port, low byte (bit 6) in 16-bit mode time-multiplexed colour-difference components U and V bidirectional expansion port, low byte (bit 5) in 16-bit mode time-multiplexed colour-difference components U and V bidirectional expansion port, low byte (bit 4) in 16-bit mode time-multiplexed colour-difference components U and V bidirectional expansion port, low byte (bit 3) in 16-bit mode time-multiplexed colour-difference components U and V bidirectional expansion port, low byte (bit 2) in 16-bit mode time-multiplexed colour-difference components U and V bidirectional expansion port, low byte (bit 1) in 16-bit mode time-multiplexed colour-difference components U and V bidirectional expansion port, low byte (bit 0) in 16-bit mode time-multiplexed colour-difference components U and V pixel qualifier input signal to mark valid pixels; expansion port horizontal sync input signal; expansion port vertical sync input signal; expansion port line-locked system clock input/output; expansion port
1996 Sep 04
14
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
115 VDDD16 114 VSSD14
104 PXQIO
125 PXQIN
112 VIDH0
111 VIDH1
110 VIDH2
109 VIDH3
108 VIDH4
107 VIDH5
106 VIDH6
105 VIDH7
128 LLCIO
handbook, full pagewidth
113 VDDD15
117 VIDL7 116 VSSD15
124 VIDL0
123 VIDL1
122 VIDL2
121 VIDL3
120 VIDL4
119 VIDL5
118 VIDL6
LLCIN VDDD1 VSSD1 VDDD2 LLC CREF HREF VS VDDD3 VSSD2 YIN0 YIN1 YIN2 YIN3 YIN4 YIN5 YIN6 YIN7 VDDD4 VSSD3 UVIN0 UVIN1 UVIN2 UVIN3 UVIN4 UVIN5 UVIN6 UVIN7 VDDD5 VSSD4 SDA SCL IICSA VDDD6 VSSD5 VDDD7 VSSD6 PORT3
103 HIO 102 VIO 101 VSSD13 100 VDDD14 99 VSSD12 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VDDD13 FDIO VRO0 VRO1 VRO2 VRO3 VRO4 VRO5 VRO6 VRO7 VRO8 VRO9 VRO10 VDDD12 VSSD11 VDDD11 VSSD10 VRO11 VRO12 VRO13 VRO14 VRO15 VRO16 VRO17 VRO18 VRO19 VRO20 VRO21 VRO22 VSSD9 VDDD10 VSSD8 VDDD9 VRO23 64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
126 HIN
127 VIN
SAA7140B
MHA359
RES
VSYV
PORT2
PORT1
PORT0
HGTV
AP
SP
FLDV
PXQV
BTST
VOEN VDDD8
VMUX VSSD7
INCADR
VCLK
HFL
VRO31
VRO30
VRO29
VRO28
VRO27
VRO26
VRO25
Fig.4 Pin configuration (SAA7140B).
1996 Sep 04
15
VRO24
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
7 FUNCTIONAL DESCRIPTION
SAA7140A; SAA7140B
In a typical application, the 16-bit wide YUV input receives clock, sync and data from a video decoder (SAA71xx) via the DMSD port. An MPEG compression/decompression circuit can be connected at the expansion port to receive the decoder data, scaled or unscaled, or to deliver data to the scaling processor. The scaling operation of the SAA7140A and SAA7140B can be performed on the data from a video decoder, or on the data from the MPEG-codec at the expansion port input. The source selection can be static or toggled on a field-by-field basis. For example, during the odd field the video decoder signal is scaled in accordance with the `odd' parameter set for display in a window. The compression codec receives unscaled data. During the even field the decompressed data from the MPEG decoder gets sized for a second display window in accordance with the `even' parameter set. The resulting output from the scaling operation is delivered via the 32-bit wide output (VRAM port) and to the expansion port output (optional). 7.1 Data format/reformatter and reference signal generation
The SAA7140A and SAA7140B accepts YUV data in a 16-bit wide parallel format at the DMSD port and accepts YUV input in a 16-bit wide parallel format and in an 8-bit byte-multiplexed Cb-Y-Cr-Y- format (CCIR-656 or D1 oriented) at the expansion port. Depending on the selected port modes, the incoming data is formatted to the internal data representation, where reference signals or codes are detected in the Data Formatter/Reformatter (DFR). The horizontal and vertical timing reference can be defined under I2C-bus control. Based on that timing reference, the active processing window is defined in a versatile way via the programming. Two programming sets can be loaded simultaneously, and become valid for processing in a field alternating way. Before being processed in the central scaling unit, the incoming data passes through the BCS control unit where monitor control functions, for adjusting brightness, contrast (luminance) and saturation (chrominance) are implemented. The scaling is performed in three steps: 1. Horizontal prescaling (bandwidth limitation for anti-aliasing, via FIR prefiltering and subsampling) 2. Vertical scaling (generating phase interpolated or vertically low-passed lines) 3. Horizontal variable phase scaling (phase-correct scaling to the new geometric relationships). The scaled output data is fed back to the DFR unit and may be used as output signals from the bidirectional expansion port (if the mode is selected). They are converted in parallel from the YUV to the RGB domain in a digital matrix. Anti-gamma correction of gamma-corrected input signals can be performed in the RGB data path. The output formatter then formats the scaled data to one of the various output formats (e.g. monochrome, 16-bit YUV or 32-bit RGB (5, 5, 5). To ease frame buffer applications, the data can be transferred in a synchronous way (transparent mode), using separate reference and qualifier signals and a continuous output clock (VCLK). The data can also be transferred in an asynchronous way (burst mode) using the HFL and INCADR flags and a discontinuous input clock burst on VCLK.
The video data can be formatted/reformatted in accordance with the selected expansion port mode, from 16-bit (DMSD port) to serial 8-bit (expansion port output), from serial 8-bit (expansion port input) to internal parallel 16-bit format and from 24-bit (scaler output) to 16-bit/8-bit respectively (expansion port output). The definition of the timing references for the acquisition and field detection (polarity and edge selection) are based on the selected reference signal source. The field detector regenerates the field information from the selected incoming reference signals (see Fig.5). The field sequence flag (FLD), detects the state of the H-sync signal at the reference edge of the V-sync signal. The detection is controlled by I2C-bus bits REVFLD and INVOE. The detection output can be seen on pins FLDV and FDIO (if FLDC = 0). Bits IREGS and SREGS control the mapping of the detected sequence to the I2C-bus register sets A and B (I2C-bus subaddress 02 to 1F and 22 to 3F).
1996 Sep 04
16
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
handbook, full pagewidth
REGISTER 00 INVOE active horizontal state REVFLD active vertical edge V source select H/V expansion port SOURCE SELECT FIELD DETECTION
REGISTER A
REGISTER B
select MULTIPLEXER active horizontal edge active vertical edge SOURCE SELECT SCALER H V (or frame sync) H/V source select
HF (corresponding to VF)
VF
H/V DMSD
AQUISITION CONTROL REGISTER 00
FIELD DETECTION (1) REGISTER SET MAPPING FIELD detected field nx
SCALER FLD IIC
MHA118
FIDO (expansion port) FLDV (VRAM)
mx
FLD detection modes (I2C-bus bits FICO1 and FICO0); (1) In the normal mode: the FLD signal is detected from the incoming H and V signals. In the improved mode: the FLD signal is resynchronized only after the H and V sequence runs stable for a certain period of time. In the force toggle mode: the FLD signal toggles with every event on the V signal (H is independent).
Register set mapping modes (I2C-bus bits IREGS and SREGS); The FLD_IIC signal carries the detected FLD or the inverted FLD. The signal is fixed to 0 (Register set A forced) or forced to 1 (Register set A forced).
Fig.5 Field detection/register set mapping.
7.1.1
DATA FORMATS AND REFERENCE SIGNALS OF THE DMSD PORT
The 16-bit YUV colour difference and luminance signals (straight binary) are available in parallel on a 16-bit wide data stream. The code is in accordance with CCIR-601; black = 16, white = 235, no colour = 128, 100% colour saturation = 16 to 240 etc. Overshoots and undershoots are permitted and supported, i.e. processed as they are. The 16-bit wide YUV data format from the DMSD port (input only) is defined with Line-Locked Clock (LLC) with a double pixel clock frequency. Every second clock cycle is qualified with CREF, in pixel rate frequency.
The internal processing of the SAA7140A and SAA7140B relies on the presence of LLC, i.e. a clock of at least twice the sampling rate of the input data stream. The maximum LLC rate is 32 MHz. The horizontal sync input (HREF) may be supplied as a H-pulse or horizontal gate signal. The positive or negative edge, (programmable by I2C-bus bit REHAW), indicates the horizontal timing reference. The first valid pixels may occur not exactly at the start of the line but with a certain offset (counted in qualified pixels).
1996 Sep 04
17
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
The vertical timing is indicated by the positive or negative edge (programmable by I2C-bus bit REVAW) of the sync input signal VS. The first valid line may occur not exactly at the start of the field but with a certain offset, counted in lines, with qualified pixels. Input signal VS defines, in relation to HREF, the odd/even field detection (see SAA7191B). 7.1.2 DATA FORMATS AND REFERENCE SIGNALS OF THE
EXPANSION PORT
SAA7140A; SAA7140B
Instead of a vertical sync signal, as described for the DMSD port, the expansion port also supports an odd/even signal applied to the input pin VIN or VIO (controlled by I2C-bus bit FSEL). The frame and the field timing is then indicated by a positive or negative edge of the V input. This may occur with a certain offset at the frame and field start, and is normally counted in lines. If the CCIR 656 data input format is selected, the vertical timing reference is decoded from the input data stream by SAV and EAV (SHVS = 1) or taken from the selected V reference signal VIN, VS or VIO (SHVS = 0). The vertical synchronization pin can be programmed to carry either a vertical sync signal or an odd/even signal. The horizontal and vertical sync outputs HIO and VIO are expansion port mode dependent and can be selected via the I2C-bus (VD1/VD0 and HD1/HD0): Should the DMSD port be selected as the output source, HIO will carry a copy of HREF and VIO will carry a copy of VS. If the expansion port carries data from the scaler output, then HIO is a gate signal enveloping the range of active video along a line and VIO is a positive sync pulse with a length of 4 lines If HIN/VIN is selected as the output source, HIO carries a copy of HIN and VIO carries a copy of VIN (short cut). If the CCIR 656 data output format is selected, the horizontal and vertical sync output signals are only supplied at pins HIO and VIO (SAV and EAV are not encoded as outputs). Due to compatibility reasons to the expansion port definition of the SAA7194/SAA7196 circuits, the bidirectional pins HIO, VIO and PXQIO can also be configured as input pins (see Table 3). The definition of the pin FDIO is I2C-bus selectable. Configured as an output pin, FDIO carries an odd/even signal generated in the FLD detection (see Fig.5). Configured as an input pin, FDIO controls the direction of the expansion port (compatibility to SAA7194/SAA7196, (see Table 3 and Chapter 8).
The expansion port (input/output) supports several modes; simultaneous (parallel) D1 input and D1 output (full duplex) with auxiliary sync and qualifying signals, or 16-bit wide YUV input or output (half duplex), selected via programming with clock, qualify and sync signal. A discontinuous data stream is supported by accepting or generating a pixel/byte qualifying signal (PXQ), a generalization of the CREF definition at the DMSD port (PXQ = 1 qualified pixel, PXQ = 0 invalid data). 16-bit YUV (half duplex mode = field alternating data I/O): 16-bit YUV data stream (Y = VIDH7 to VIDH0, UV = VIDL7 to VIDL0). For the 16-bit YUV data input format, PXQ is inhibited from qualifying adjacent LLC clock cycles. There must be at least one empty clock cycle between two valid pixels. 8-bit Cb-Y-Cr-Y; CCIR 656 or D1 (full duplex mode): the colour difference signals and the luminance signal (straight binary) are byte-wise multiplexed onto the same 8-bit wide data stream, with sequence and timing in accordance with CCIR 656 recommendations (according to D1 for 60 Hz application respectively). The code is in accordance with CCIR 601 (black = 16, white = 235, no colour = 128, 100% colour saturation = 16 or 240, etc. Overshoots and undershoots are permitted and supported, i.e. processed as they are. If the CCIR 656 output is selected, the video signal is clipped to 01H and FEH in order to leave the codes 00H and FFH for SAV and EAV encoding (SAV and EAV encoding not yet supported). The clock rate for this format is twice the pixel clock. The horizontal sync input HIN is processed in an identical manner to HREF at the DMSD port. If the CCIR 656 data input format is selected, the horizontal timing reference is decoded from the input data stream (SAV, EAV and SHVS = 1) or taken from the selected H-reference signal HIN, HREF or HIO (SHVS = 0). The start condition to enable synchronization to the correct Cb-Y-Cr-Ysequence is provided by the selected horizontal reference signal. The sequence only increments with qualified bytes.
1996 Sep 04
18
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
handbook, full pagewidth
LLC
CREF
PXQIN
VIDL7 to 0
Cb0
Cr0
Cb2
Cr2
VIDH7 to 0
Y0
Y1
Y2
Y3
HIN
MHA126
Fig.6 Timing of PXQIN for 16-bit data input from DMSD to expansion port.
handbook, full pagewidth
LLC
CREF
PXQIN
VIDL7 to 0
Cb
Y
Cr
Y
Cb
Y
HIN
MHA130
Fig.7 Timing of PXQIO for serial 8-bit data input at expansion port.
1996 Sep 04
19
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
handbook, full pagewidth
LLC
CREF
PXQIN/PXQIO
VIDL7 to 0
FFH
00H
00H
SAV
Cb
Y
Cr
PXQIN/PXQIO
VIDL7 to 0
Y
Cr
Y
FFH
00H
00H
EAV
MHA129
Fig.8 Timing of PXQIN/PXQIO for CCIR 656 data input at expansion port.
handbook, full pagewidth
LLC
CREF
PXQIO
VIDL7 to 0
Cb0
Cr0
Cb2
Cr2
VIDH7 to 0
Y0
Y1
Y2
Y3
HIO
MHA127
Fig.9 Timing of PXQIO for non-zoomed 16-bit data output at expansion port.
1996 Sep 04
20
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
handbook, full pagewidth
LLC
CREF
PXQIO
VIDL7 to 0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
Cb6
Cr6
VIDH7 to 0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
HIO
MHA128
Fig.10 Timing of PXQIN for zoomed 16-bit data output at expansion port.
handbook, full pagewidth
LLC
CREF
PXQIO
VIDL7 to 0
Cb
Y
Cr
Y
Cb
Y
Cr
Y
HIO
MHA131
Fig.11 Timing of PXQIO for serial 8-bit data output at expansion port.
1996 Sep 04
21
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
7.2 Acquisition control
SAA7140A; SAA7140B
one qualified pixel. Depending on the selected mode, the source for the horizontal reference may be HREF (DMSD port) or HIN (expansion port), or for the vertical reference, VS (DMSD port) or VIN (expansion port). It should be noted that in order to avoid programming dependent line and field drop effects, all values must not exceed the number of qualified pixels per line or lines per field.
The processing window for the scaling unit is defined in the acquisition control unit. An internal counter receives I2C-bus controlled values for offset (bits XO10 to XO0 and YO10 to YO0) and length (bits XS10 to XS0 and YS10 to YS0). The counter is reset by the corresponding sync reference input signal. The horizontal counter increments in qualified pixels and the vertical counter increments in qualified lines, i.e. lines containing at least
handbook, full pagewidth
HIN/HREF PXQ/CREF
ACTIVE VIDEO WINDOW xo yo xs
VIN/VS ys LQ (1) SCALING WINDOW
field/ frame
line PXQV output signals HGTV (1) LQ = qualified lines i.e. lines containing at least one qualified pixel.
MHA119
Fig.12 Reference signals for scaling window.
7.3
BCS control
For the contrast control: 00H = luminance off 40H = nominal gain of 1.01 7FH = maximum gain of 1.9999. The chrominance signal can be controlled via the I2C-bus using bits SAT6 to SAT0. For the saturation control: 00H = colour off 40H = nominal gain of 1.0 7FH = maximum gain of 1.9999.
The parameters for Brightness, Contrast and Saturation (BSC) can be adjusted in the BSC control unit. The luminance signal can be controlled via the using bits BRIG7 to BRIG0 and CONT6 to CONT0. For the brightness control: 00H = minimum offset 80H = nominal level FFH = maximum offset. I2C-bus
1996 Sep 04
22
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
With respect to limiting, all values are limited to minimum (equals 0) and maximum (equals 255). 7.4 Scaling unit
SAA7140A; SAA7140B
Figures 13 and 14 illustrate some frequency responses and the corresponding I2C-bus settings. The prefilter operates on 4 : 4 : 4 YUV data. As U and V are generated by simple chroma pixel doubling, the UV prefilter should also be used to generate the interpolated chroma values.
Scaling to a randomly sized window is performed in three steps: 1. Horizontal prescaling (bandwidth limitation for anti-aliasing, via FIR prefiltering and subsampling) 2. Vertical scaling (generating phase interpolated or vertically low-passed lines) 3. Horizontal variable phase scaling (phase-correct scaling to the new geometric relations). The scaling processor can obtain its clock from the DMSD port or the expansion port. Normally the two ports are synchronized to support program-set-swapping, asynchronous working results in restricted operation. The video signal source also provides the source for the scalers qualify signal PXQ. The scaling process generates a new pixel/clock qualifier sequence. This results in PXQ being used at the VRAM port in the transparent mode, and for the expansion port output. There are restrictions in the combination of the input sample rate and up or down-scaling mode and scaling factor. The maximum resulting output sample rate at the VRAM port is LLC and at the expansion port the maximum pixel rate is 12LLC, due to the support of the CCIR 656 format. 7.4.1 HORIZONTAL PRESCALING
7.4.1.2
Subsampler
To improve the scaling performance for scales of less than 12 down to icon size, a FIR filtering subsampler is available. It performs a subsampling of the incoming data by a factor of 1/N (where N = XPSC + 1 = 1 to 64). With NIP equalling the number of input pixel/line and NOP equalling the number of desired output pixels/line, the basic equation to calculate XPSC is as follows: N IP XPSC = TRUNC x ------------------- N OP - 1 The subsampler collects a number of [N + 1(-XACM)] pixels to calculate a new subsampled output pixel. Consequently, a downscale dependent FIR filter has been incorporated, with up to 65 taps, which reduces aliasing for small sizes. If XACM = 0 the collecting sequence overlaps, which means that the last pixel of sequence M is also the first pixel of sequence M + 1. To implement a real subsampler bypass XACM has to be set to logic 1. It should be noted that because the phase-correct horizontal fine scaling is limited to a maximum downscale of 14, this circuitry has to be used for downscales less than 14 of the incoming pixel count. To obtain unity gain at the subsamplers output for all subsampling ratios, the I2C-bus parameters CXY, CXUV and DCGX have to be used. In addition, the I2C-bus parameters can be used to slightly modify the FIR characteristic of the subsampler. Table 1 gives examples of I2C-bus register settings, depending on a given prescaler ratio. With reference to Table 1, it should be noted that an internal XPSC-dependent automatic prenormalization becomes valid for XPSC > 8, > 6 and >32, which reduces the input signal quantization. In addition, for XPSC 15 the LSB of the CXY and CXUV parameter become valid.
The incoming pixels in the selected range are preprocessed in the horizontal prescaler, which is the first stage of the scaling unit. The prescaler consists of an FIR prefilter and a pixel collecting subsampler.
7.4.1.1
FIR prefilter
The video components Y, U and V are FIR prefiltered to reduce the signal bandwidth in accordance with the downscale for factors between 1 to 12, thus aliasing due to signal bandwidth expansion is reduced. The prefilter consists of 3 filter stages. The transfer functions are given in Chapter 8. The prefilter is controlled by the I2C-bus bits PFY3 to 0 and PFUV3 to 0 in I2C-bus subaddress 13 and 33.
1996 Sep 04
23
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
handbook, full pagewidth
18
MHA121
(Gain) dB 6 0 -6
(1)
(2)
-18
-30
(3) (5) (4)
-42 0 0.1 0.2 0.3 0.4 f fclk 0.5
I2C-bus bytes PFY3 to PFY0. (1) = 0001; (2) = 0010; (3) = 0011; (4) = 1011; (5) = 1111.
Fig.13 Luminance prefilter frequency response for miscellaneous I2C-bus settings.
MHA122
handbook, full pagewidth
18
(Gain) dB 6 0 -6
(1)
-18
(6)
(5)
(2)
-30
(4) (3)
-42 0 0.1 0.2 0.3 0.4 f fclk 0.5
I2C-bus bytes PFU3 to PFU0. (1) = 0001; (2) = 0010; (3) = 1010; (4) = 1110; (5) = 0011; (6) = 1111.
Fig.14 Chrominance prefilter frequency response for miscellaneous I2C-bus settings.
1996 Sep 04
24
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
Table 1 Horizontal prescaling and normalization COEFFICIENT SEQUENCE (example) 1-1 1-1-1 1-2-1
3 1 4 1 5 1
SAA7140A; SAA7140B
HORIZONTAL XPSC PRESCALING 1
1 2
CXY (luma)/ CXUV (chroma) (HEX) 00 00 02 00 00 06 00 02 04 00 08 00 00 1E 00 16 1C 00 2A 38 00 12 30 00 44 60 00 10 40 00 80 00 FF 00 FE DF
WEIGHT SUM 2 3 4 4 5 8 6 8 8 7 8 8 9 16
10 2 16 2 16 2 11 2 16 2 16 2 12 2 16 2 16 2 13 2 16 2 16 2 14 2 16 2 16 2 15 2 16 2 16 2 17 2 32 2 18 4 32 4 32 4
DCGX 1 1 2 2 2 3 2 3 3 3 3 3 3 7 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 3 7 2 3 3
BSC (CONT/SAT) = x/y x 64 1
2 3
0 1 2 3 4
1 1
4 5
1-1-1-1 1-1-1-1-1 1-2-2-2-1 111 111 121 121 112 211
1
4 6
1 1
8 7
1 6 1 7 1 8 1 9
5 6 7 8
111 1 111 111 2 111 1111 1111 1111 1 1111 1222 2 2221 1111 1 1 1111 1221 2 2 1221 1122 2 2 2211
1 1
8 9
1
4 5
1 1
8 11
1
10
9
1111 1 1 1 1111 1212 1 2 1 2121 1112 2 2 2 2111
1 1
8 12
1
11
10
1111 11 11 1111 1211 21 12 1121 1111 22 22 1111
1 1
8 13
1
12
11
1111 11 1 11 1111 1121 11 2 11 1211 1111 12 2 21 1111
1 1
8 14
1
13
12
1111 111 111 1111 1111 211 112 1111 1111 112 221 1111
1 1
8 15
1 1 1 1
14
13 14 15 16
1111 111 1 111 1111 1111 111 2 111 1111 1111 1111 1111 1111 1111 1111 1 1111 1111 1222 2222 2 2222 2221 1111 1111 1 1 1111 1111 1222 2222 1 1 2222 2221 1222 2122 22 2212 2221
1 1
16 17
15 16
1
16 18
17
1 1
1996 Sep 04
25
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
HORIZONTAL XPSC PRESCALING
1 18
COEFFICIENT SEQUENCE (example) 1111 1111 1 1 1 1111 1111 1222 1222 1 2 1 2221 2221 1222 2112 2 2 2 2112 2221
CXY (luma)/ CXUV (chroma) (HEX) 00 EE 9F .... 00 .... .... ....
WEIGHT SUM
19 4 32 4 32 4 xx 4 34 8 xx 8
DCGX 2 3 3 .... 2 .... .... ....
BSC (CONT/SAT) = x/y x 64
16 19
17
1 1 .... - .... .... ....
....
1 1 1 33
.... 32 .... 62 63
.... 1111 ... 1111 .... .... ....
....
63 64
.... ....
7.4.2
VERTICAL SCALER
The vertical scaler performs the vertical downscaling of the input data stream to a random number of output lines. It can be used for input line lengths up to 768 pixels/line and has to be bypassed if the input line length exceeds the pixel count. For vertical scaling there are two different modes implemented; the ACCU mode (vertical accumulation) for scales down to icon size and the Linear Phase Interpolation mode (LPI) for scales between 1 and 12.
N IL YACL = TRUNC x ------------------- ; N OL - 1 accumulation sequence length: i.e. the number of lines per sequence that are not part of overlay region of neighbouring sequences (optimum 1 line overlapped). 1 - N OL YSCI = INT 1024 x ------------------- ; scaling increment. N IL YSCI YP = INT -------------- ; scaling start phase (fix; modified in 16 - LPI mode only). In order to obtain unity amplitude gain for all sequence lengths and to improve the vertical scaling performance, the accumulated lines can be weighted and the amplitude of the scaled output signal has to be renormalized. In the given example (see Fig.15) using the optimum weighting, the gain of a sequence results in 1 + 2 + 2 + 1 = 6. Renormalization (factor 1/6) can be achieved; By gain reduction using BCS control (brightness, contrast and saturation) down to 46 and a selecting factor of 14 for DCGY2 to DCGY0 (see Section 8.3), which may result in a loss of signal quantization, or By gain emphasizing using BCS control up to 86 and selecting a factor of 18 for DGY2 to DCGY0 which may result in a loss of signal detail, due to limiting in the BCS control. Normally the weighting would be 2 + 2 + 2 + 2. In this situation the gain can be renormalized with DCGY2 to DCGY0 = 010 (factor 18). Table 2 gives examples for I2C-bus register settings, depending on a given scale ratio.
7.4.2.1
ACCU mode (scaling factor range 1 to 1/1024; I2C-bus bit YACM = 1:
The ACCU mode can be used for vertical scaling down to icon size. In this mode, the I2C-bus parameter YSCI controls the scaling and parameter YACL controls the vertical anti-alias filtering. The output lines are generated by a scale-dependent variable averaging (YACL + 2) input lines. In this way a vertical FIR filter can be created for anti-aliasing, with up to 65 taps (max.). YSCI defines the output line qualifier pattern and YACL defines the sequence length for the line averaging. For accurate processing, the sequence has to fit into the qualifying pattern. In the event of mis-programming YACL unexpected line dropping occurs; where NOL = number of output lines and NIL = number of input lines. The I2C-bus bits YSCI (scaling increment), YACL (accumulation length; optimum: 1 line overlap) and YP (scaling start phase) have to be set according to the following equations (see Fig.15):
1996 Sep 04
26
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
handbook, full pagewidth
optimal weighting factors: line 1 line 2 1st sequence 2nd sequence 3rd s equence line 10
1 2 2 1 2 2 1 2 2 1
YACL = INT{(1-S)/S}
= 2 (dotted lines)
YSCI = INT{(1024 x (1-S)} = 682 YP = INT{YSCI/16} = 42
MHA120
Fig.15 Example of vertical accumulation.
Table 2
Vertical scaling and normalization YACL 0 1 2 3 4 COEFFICIENT SEQUENCE (example) 1-1 1-1-1 1-2-1 1-1-1-1 1-1-1-1-1 1-2-2-2-1 111 111 121 121 112 211 5 6 7 8 111 1 111 111 2 111 1111 1111 1111 1 1111 1222 2 2221 1111 1 1 1111 2121 2 2 1212 1122 2 2 2211 9 1111 1 1 1 1111 1212 1 2 1 2121 1112 2 2 2 2111 10 1111 11 11 1111 1211 21 12 1121 1111 22 22 1111 CYA (HEX) 01 03 01 03 07 01 07 05 03 0F 07 0F 1F 01 1F 09 03 3F 15 07 3F 2D 0F CYB (HEX) 00 00 02 00 00 06 00 02 04 00 08 00 00 1E 00 15 1C 00 2A 38 00 12 30 WEIGHT SUM 2 3 4 4 5 8 6 8 8 7 8 8 9 16 10 16 16 11 16 16 12 16 16 DCGY 0 0 1 1 1 2 1 2 2 2 2 2 2 3 3 3 3 2 3 3 2 3 3 BCS (CONT/SAT) = x/y x 64 1
2 3
VERTICAL SCALE RATIO (YSCI ) 1 to 12 (0)
1 2 1 3 1 4 1 5
to 13 (512) to 14 (683) to 15 (768) to 16 (820) to 17 (854) to 18 (878) to 19 (896) to 110 (911)
1 11
1 1
4 4 5
1
6
1 1
8 7
1 6 1 7 1 8 1
1 1
8 8 9
1
10
9
1 1
8 11
1 10
to (922)
1 1
8 12
1 11
to 12 (931)
1
1 1
1996 Sep 04
27
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
VERTICAL SCALE RATIO (YSCI )
1 12
YACL 11
COEFFICIENT SEQUENCE (example) 1111 11 1 11 1111 1111 21 2 12 1111 1121 11 2 11 1211
CYA (HEX) 7F 2F 3B 7F 6F 3F FF 7F FF FF 02 FF 44 01 .... 0F AD
CYB (HEX) 00 50 44 00 10 40 00 80 00 00 FD 00 BB FE .... F0 52
WEIGHT SUM 13 16 16 14 16 16 15 16 16 17 32 18 32 32 .... 32 32
DCGY 2 3 3 2 3 3 2 3 3 3 4 3 4 4 .... 4 4
BCS (CONT/SAT) = x/y x 64
8 13
to 113 (939) to 114 (946)
1 15
1 1
8 14
1
13
12
1111 111 111 1111 1111 211 112 1111 1111 112 211 1111
1 1
8 15
1 1 1 1
14
to (951)
13 14 15 16
1111 111 1 111 1111 1111 111 2 111 1111 1111 1111 1111 1111 1111 1111 1 1111 1111 2122 2222 2 2222 2212 1111 1111 1 1 1111 1111 2212 2212 2 2 2122 2122 1222 2222 1 1 2222 2221
1 1
16 16 17
15
to 116 (956) to 117 (960) to 118 (964)
16
1
18
17
1 1 .... 1 1
....
1 1 23 to 24 (980)
.... 22
.... 1111 2222 1111 1111 2222 1111 1121 1212 1121 1211 2121 1211
7.4.2.2
LPI mode (scaling factor range 1 to 12; IC-bus bit YACM = 0)
input lines N distance = 1 M A A-1
MHA361
To preserve the signal quality for slight vertical downscales (scaling factors 1 to 12) linear phase interpolation between consecutive lines is implemented to generate geometrically correct vertical output lines.Therefore, the new geometric position between lines N and N + 1 can be calculated. A new output line is calculated by weighting the samples `p' (pixel) of lines N and N + 1 with the normalized distance to the new calculated position (see Fig.16); When NOL = number of output lines and NIL = number of input lines the I2C-bus bits YSCI (scaling increment) and YP (scaling start phase) have to be set according to the following equations;
handbook, halfpage
N+1
new calculated position of output line M
p ( M) = A x p ( N + 1) + ( 1 - A) x p ( N) where A = 0 to 63/64
Fig.16 New output line calculation.
1996 Sep 04
28
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
N IL YSCI = INT 1024 x ---------- - 1 N OL
SAA7140A; SAA7140B
The phase scaling consists of a filter and arithmetic structure with 10 taps for the luminance and 4 taps for the chrominance processing. It is able to generate a phase-correct new pixel value, with virtually no phase or amplitude artefacts. The new samples are calculated with a phase accuracy of 164 of the pixel distance. When using this circuit the up and down scaling is controlled by the I2C-bus parameters XSCI and XP. Because the variable phase scaling is restricted to downscale >14 of the fine scalers input pixel count, XSCI is also a function of the prescaling parameter XPSC. As NIP = number of input pixels per line (at SAA7140A input) and NOP = number of desired output pixels/line, XSCI is defined by the following equation: N IP 1024 XSCI = INT ---------- x --------------------------------N OP ( XPSC + 1 ) The maximum value of XSCI = 4095. Zooming is performed for XSCI values less than 1024. The number of disqualified clock cycles between consecutive pixel qualifiers (at the phase scalers input) defines the maximum possible zoom factor. This means that zooming may also be a function of XPSC. It should be noted that implementation is dependent on a zooming factor greater than 2. Some artefacts may occur at the end of the zoomed line. Internal rounding effects, may result in a deviation of 1 output pixels compared to the expected result. In this situation, the I2C-bus parameter XP can be used to shift the starting phase of the phase calculation and thereby force an additional cycle to be disqualified. In addition, when XP 128 it will force the internal phase calculation to fixed values, especially when XP = 128 it will force the phase scaler into bypass. The scaled output data is fed back to the data formatter/reformatter unit and may be used as output signals from the bidirectional expansion port (if the mode is selected). 7.5 Colour Space Matrix (CSM), dither and gamma correction
; scaling increment
YSCI YP = INT -------------- ; scaling start phase 16 - (recommended value). The vertical start phase offset is defined by YP64 (YP = 0 to 64): YP = 0: offset = 0 geometrical position of 1st line out = 1st line in. YP = 64: offset = 6464 = 1 geometrical position of 1st line out = 2nd line in. Finally 3 special modes must be emphasized: 1. By-pass (YSCI = 0, YP = 64) each line out is equivalent to corresponding line in. 2. Low-pass (YSCI = 0, YP < 64) e.g. YP = 32: average value of 2 lines (1 + z -H filter). 3. For processing of interlaced input signals the LPI mode must be used (the ACCU mode would cause `line pairing' problems). The scaling start phase for odd and even field have to be set to: YSCI YP even = YP odd + -------------- ; 32 where line 1 = odd. In modes 1 and 2 the first input line is fed to the output (without processing) so that the number of output lines equals the number of input lines.
7.4.2.3
Flip option (FLIP = 1)
For both vertical scaling modes there is a flip option (mirroring) available for input lines with a maximum of 384 pixels. In the event that full screen pictures (e.g. 768 x 576) are to be flipped, they first have to be scaled down to 384 pixels per line in the horizontal prescaling unit. After vertical processing (flipping) they can be rezoomed to the original 768 pixels per line in the following VPD. It should be noted that when using the flip option, the last input line can not be displayed at the output. 7.4.3 HORIZONTAL VARIABLE PHASE SCALING
In the phase-correct horizontal variable phase scaling the pixels are calculated for the geometrical correct, orthogonal output pattern, down to 14 of the prescaled pattern. In addition, a horizontal zooming feature is supported. The maximum zooming factor is at least 2, thus being even more dependent on input pattern and prescaling settings.
The scaled YUV output data can be converted after Interpolation into RGB data in accordance with CCIR 601 recommendations.
1996 Sep 04
29
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
The matrix equations considering the digital quantization are as follows; R = Y + 1.375 V G = Y - 0.703125 V - 0.34375 U B = Y + 1.734375 U For error diffusion a dither algorithm of the 5-bit truncation error RGB (5, 5, 5) is implemented. An anti-gamma characteristic ( = 1.4) is implemented at the matrix output to provide anti-gamma correction of the RGB data. The curve can be used (bit RTB = 0) to compensate gamma correction for linear data representation of the RGB output data. The chroma signal keyer generates an alpha signal to achieve an RGB (5, 5, 5) + output signal. Therefore, the processed UV data amplitudes are compared with thresholds set via the I2C-bus. A logic 1 signal is generated if the amplitude is within the specified amplitude range, if the amplitude is outside the specified range a logic 0 is generated. Keying can be switched off by setting the lower limit higher than the upper limit. For 16-bit YUV data formats or monochrome modes the CSM block is bypassed. 7.6 Output formatter and output FIFO register
SAA7140A; SAA7140B
7.6.1.2 24-bit RGB:
The resampled YUV samples are converted into RGB (8 bits each). All three components have the same sample rate as luminance Y. Anti-gamma correction is available (programming). The alpha bit is generated as the chroma key in the UV domain. Two RGB representations (code meanings) are supported: 1. The CCIR 601 orientated RGB representation defines code 16 for black and code 235 for full saturation. 2. The graphics display orientated RGB representation codes black with 00H and white with FFH. This representation can be achieved by corresponding programming of brightness (equals offset), contrast and saturation (equals gain) in the YUV domain. This format is used in the transparent mode and in the FIFO mode (one pixel at a time).
7.6.1.3
15-bit RGB (5, 5, 5) + in 2 bytes
In order to support various scaling applications, the output data at the VRAM port can be delivered in different formats and different transfer modes. Besides the 16-bit YUV format (see Section 7.1.1) the VRAM port also supports the data formats 24-bit RGB, 2 x 15-bit RGB + or 8-bit grey scale. Should the synchronous data transfer mode (transparent mode) be selected, the VRAM port will provide VCLK clock (clock rate of LLC) and PXQ (polarity via programming) on extra pins for use by the circuitry receiving the VRAM port data stream. To ease frame buffer applications, an asynchronous transfer (burst or FIFO mode) can be selected. In this mode the VRAM ports VCLK has to be provided from an external source, with a maximum clock rate of 32 MHz. Only valid data is collected and transported. 7.6.1 DATA FORMATS AND REFERENCE SIGNALS OF THE VRAM PORT
The resampled YUV samples are converted into 24-bit RGB. The following truncation to 5 bits is optionally (programming) performed with dithering effect (error diffusion). There are two representations (code meanings) supported; CCIR and graphics display orientated (see Section 7.6.1.2). The alpha bit is generated as chroma key in the YUV domain. This format is used in the transparent mode and in the FIFO mode (one pixel at a time, or two pixels at a time). The ordering of RGB bits and bytes at the VRAM port is identical to that of the SAA7196.
7.6.1.4
8-bit grey scale
This is simply a Y = luminance signal which can be selected to be coded as binary, or all bits inverted. This format is used in the transparent mode and in the FIFO mode (1, 2 or 4 pixels at a time). The horizontal sync output HGTV marks (source independent) the range of the active video at the VRAM port. The vertical sync output VSYV (I2C-bus controlled polarity) carries the vertical sync information for the VRAM port output data (positive or negative pulse with a length of 4 lines). At the falling or rising edge of VSYV the FLDV output is stable.
7.6.1.1
16-bit YUV (see Section 7.1.1)
The ordering of YUV bits and bytes at the VRAM port is identical to that of the SAA7196.
1996 Sep 04
30
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
PIXCLK handbook, full pagewidth (LLC/2)
FIFO memory filling level
7
8
9
8
8
7
6
6
5
4
4
HFL minimum 8 words available in FIFO maximum 32LLC(1) (16 PIXCLK) 1 transfer cycle (8 VCLK cycles)
VCLK
VOEN
VRO(n)
7
0
1
2
3
4
5
6
7
MHA132
If VCLK cycles occur at VOEN = HIGH the FIFO register is unchanged but the outputs VRO31 to VRO0 remain in the 3-state position. (1) Only valid for non-zoomed data.
Fig.17 Output port transfer to VRAM at 32-bit data format without scaling.
handbook, full pagewidth
line n INTERNAL SIGNAL active video
line n + 1 vertical blanking
last half-full request for line n (1) HFL
64LLC
minimum set-up time
MHA123
INCADR
64LLC 10LLC
(1) line increment sequence (1)
vertical reset pulse
(1) Only available for interfaced processing at the beginning of an odd field.
Fig.18 Vertical reset timing of the VRAM port.
1996 Sep 04
31
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
7.7 7.7.1 Data transfer modes EXPANSION PORT MODES
SAA7140A; SAA7140B
* Does the application require separate input and output reference signal lines, if yes then I2C-bus bit SRIO = 0 * Does the application need hardware controlled I/O switching, if yes then I2C-bus bit FLDC = 1 and use of pin FDIO or * Does software controlled I/O switching (register set controlled) the same job, if yes then I2C-bus bit FLDC = 0 * Which signal path defines the clock system * Which signal path is the synchronization master * Is dynamic field-wise switching required or is the source switching quite static, if static then do not be confused about odd or even; use SREGS and IREGS before referring to the I2C-bus section.
The expansion port is controlled by I2C-bus subaddresses 02 (22H) and 03 (23H). The expansion port can be configured in a very flexible way. Table 3 gives examples of the I2C-bus programming for several expansion port configurations. SAA7196 compatible modes are marked as `xx96' in the MODE column. After reset the expansion port reference signal inputs are set to the `xxIO' pins. After reset the expansion port reference signal inputs are set to the `xxIO' pins. Pin FDIO can be used in the same way as the DIR pin of the SAA7196 if the I2C-bus bit FLDC is set to logic 1. More information concerning the control signals can be found in Chapter 8. For correct application the user should first decide about some global interface properties before referring to this chapter such as:
1996 Sep 04
32
Table 3 SCALER INPUT CONTROL [SUBADDRESS 03 (23H)] I/O VD1 0 0 X X 1 1 0 1 0 X 0 0 x x 0 0 0 0 X X X 0 0 X X X 0 1 1 0 X X X 0 1 X X 1 0 0 1 1 0 0 0 X X X X X 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 X X X X X 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 X 1 0 0 0 1 1 1 0 1 x 1 0 1 0 1 1 1 1 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 note 15 note 16 note 17 note 18 0 0 0 0 0 0 0 0 1 0 note 2 0 0 0 0 0 0 0 0 0 0 note 1 VD0 HD1 HD0 PXQD LLCD SRIO VSI HSI VIPSI LLCS
Expansion port programming examples
1996 Sep 04
DAVE OUTPUT CONTROL [SUBADDRESS 02 (22H)]
MODE
FDIO
YUV8 04 to 24H
FLDC
VIDC
Philips Semiconductors
0
X
0
0
0
1
X
0
0
1
2
X
0
0
1
3
X
0
0
1
4
X
0
0
0
5
X
1
0
0
6
X
1
0
0
High Performance Scaler (HPS)
7
X
1
0
0
8
X
0
0
1
9
X
1
0
1
0 '96
0
0
1
0
33
1 '96
1
0
1
0
2 '96
1
0
1
1
3 '96
x
0
1
1
4 '96
1
0
1
1
5 '96
0
0
1
0
6 '96
1
0
1
0
Notes
1. Scaler input from LLC, Y/UVIN, CREF, HREF and VS; expansion port output clock, data, qualifier, horizontal and vertical reference derived from LLC, Y/UVIN, CREF, HREF and VS.
2. Scaler input from LLC, VIDH|L, PXQIN, HREF and VS; expansion port output clock, data, qualifier, horizontal and vertical reference derived from LLC, d.c., CREF, HREF and VS.
3. Scaler input from LLCIN, VIDH|L, PXQIN, HIN and VIN; expansion port output clock, data, qualifier, horizontal and vertical reference derived from LLCIN, d.c., CREF, HIN and VIN.
SAA7140A; SAA7140B
Objective specification
4. Scaler input from LLC, VIDH|L, PXQIN, HIN and VIN; expansion port output clock, data, qualifier, horizontal and vertical reference derived from LLC, d.c., CREF, HIN and VIN.
5. Scaler input from LLC, Y|UVIN, CREF, HREF and VS; expansion port output clock, data, qualifier, horizontal and vertical reference derived from LLC, YUVsc, Psc, Hsc and Vsc.
1996 Sep 04
6. Scaler input from LLC, VIDL, PXQIN, HREF and VS; expansion port output clock, data, qualifier, horizontal and vertical reference derived from LLC, YUVsc->VIDH, Psc, Hsc and Vsc.
Philips Semiconductors
7. Scaler input from LLCIN, VIDL, PXQIN, HIN and VIN; expansion port output clock, data, qualifier, horizontal and vertical reference derived from LLC, Y|UVIN->VIDH, C+HREF and VS.
8. Scaler input from LLCIN, VIDL PXQIN, HIN and VIN; expansion port output clock, data, qualifier, horizontal and vertical reference derived from LLCIN, YUVsc->VIDH, Psc, Hsc and Vsc.
9. Scaler input from LLC, VIDH|L PXQIN, HIN and VS; expansion port output clock, data, qualifier, horizontal and vertical reference derived from LLC, d.c., CREF, HREF and VS.
10. Scaler input from LLCIO, VIDH, PXQIO, HIO and VIO; expansion port output clock, data, qualifier, horizontal and vertical reference derived from d.c., d.c., d.c., d.c. and d.c..
11. Scaler input from LLC, Y|UVIN, CREF, HREF and VS; expansion port output clock, data, qualifier, horizontal and vertical reference derived from LLC, Y|UVIN, CREF, HREF and VS.
High Performance Scaler (HPS)
12. Scaler input from LLC, VIDH|L, CREF, HREF and VS; expansion port output clock, data, qualifier, horizontal and vertical reference derived from LLC, d.c., CREF, HREF and VS.
13. Scaler input from LLCIO, VIDH|L, PXQIO, HIO and VIO; expansion port output clock, data, qualifier, horizontal and vertical reference derived from d.c., d.c., d.c., d.c. and d.c..
34
14. Scaler input from LLC, VIDH|L, CREF, HIO and VIO; expansion port output clock, data, qualifier, horizontal and vertical reference derived from LLC, d.c., CREF, d.c. and d.c.
15. Scaler input from LLC, VIDH/L, PXQIO, HIO and VS; expansion port output clock, data, qualifier, horizontal and vertical reference derived from LLC, d.c., d.c., d.c., HREF and VS.
16. Scaler input from LLC, Y/UVIN, CREF, HREF and VS; expansion port output clock, data, qualifier, horizontal and vertical reference derived from LLC, Y/UVIN, CREF, HREF and VS.
17. Scaler input from LLCIO, VIDH/L, PXQIO, HREF and VS; expansion port output clock, data, qualifier, horizontal and vertical reference derived from d.c., d.c., d.c., HREF and VS.
SAA7140A; SAA7140B
18. Fill in user specific configuration.
Objective specification
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
7.8 7.8.1 VRAM port modes DATA BURST TRANSFER MODE (FIFO MODE)
SAA7140A; SAA7140B
The SAA7140A and SAA7140B delivers a continuously processed data stream. Consequently, the extended formats of the VRAM port output are selected (bit FS2 = 1; see Tables 6 and 7). The output reference signals have to be used to buffer qualified preprocessed RGB or YUV video data. The YUV data is only valid in qualified time slots. Control output signals (see Tables 6 and 7) are: * = keying signal of the chroma keyer (not on extra pin but in lower byte of VRO output) * FLDV = odd/even field bit in accordance with the internal field processing * VSYV = vertical sync signal, active polarity is defined by VSYP bit * HGTV = horizontal gate signal, logic 1 marks the horizontal direction from XO to (XO + XS) lines * PXQV = pixel qualifier signal, active polarity is defined by QPP bit. Interlaced processing (OF bits, subaddress 01): to support correctly interlaced data storage, the scaler delivers two INCADR/HFL sequences in each qualified line and an additional INCADR/HFL sequence after the vertical reset sequence at the beginning of an odd field. Consequently, the scaled lines are automatically stored in the right sequence. INCADR timing: the distance from the last half-full request (HFL) to the INCADR pulse may be longer than 64LLC. The state of HFL is defined for minimum 2LLC cycles afterwards. Monochrome format (see Tables 6 and 7); If TTR = 1 and FS2 = 1 then Ya = Yb. 7.8.3 I2C-BUS CONTROLLED PSEUDO SLEEP MODE
Data transfer on the VRAM port is asynchronous (TTR = 0). This mode can be used for all output formats. Four signals for communication with the external memory are provided: 1. HFL flag: the half-full flag of the FIFO output register is raised when the FIFO contains at least 8 data words (HFL = HIGH). By setting HFL to logic 1, the SAA7140A and SAA7140B requests a data burst transfer, via the external memory controller, that has to start a transfer cycle within the next 32LLC cycles for 32-bit long word modes (16LLC cycles for 16 and 24-bit modes). If there are pixels in the FIFO at the end of the line, which are not transferred, the circuit fills up the FIFO register with `fill pixels' until it is half-full and sets the HFL flag to request a data burst transfer. After the transfer is completed, HFL is used in combination with INCADR to indicate the line increments. 2. The INCADR output signal is used in combination with HFL to control horizontal and vertical address generation for a memory controller. The pulse sequence depends on field formats (interlace/non-interlace or odd/even fields) and control bits OF1 and OF0 (subaddress 01). This means that: a) HFL = 1 at the rising edge of INCADR: the END OF LINE is reached; request for line address increment b) HFL = 0 at the rising edge of INCADR: the END OF FIELD/FRAME is reached; request for line and pixel address reset 3. VCLK input signal to clock the FIFO register output data VRO(n). New data is placed on the VRO(n) port with the rising edge of VCLK (see Fig.17). 4. The VOEN input enables output data VRO(n). The outputs are in 3-state mode at VOEN = HIGH. VOEN changes only when VCLK is LOW. If VCLK pulses are applied when VOEN is HIGH, the outputs remain inactive but the FIFO register accepts the pulses. 7.8.2 CONTINUOUS DATA TRANSFER MODE (TRANSPARENT
MODE)
To reduce the power consumption of the SAA7140A and SAA7140B during phases, where no scaling operations are requested in the application, it is possible to switch the SAA7140A and SAA7140B into a pseudo sleep mode. This mode can be activated, if the clock input LLCIN is not used or if the hardware is able to pull the LLCIN input or the LLCIO pin (in input mode) down to logic 0. In applications, which do not use LLCIN, then LLCIN should be connected to ground. LLC has to be provided continuously.
Data transfer on the VRAM port can be achieved synchronously (TTR = 1), controlled by output reference signals at separate pins (except the -signal) and a continuous clock output signal (clock rate of LLC) on the VCLK pin. 1996 Sep 04 35
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
To activate the `Sleep Mode' the scalers processing has to be switched to one of the inactive clock inputs of the expansion port. For example, If LLCIO is used as input and output in the application then: LLCIN grounded => `Sleep Mode' is active, if I2C-bus bits FLDC = 0, SRIO = 0 and LLCS = 1. and If LLCIN is used as input and LLCIO is used as output: LLCIN pulled down => `Sleep Mode' is active, if I2C-bus bits FLDC = 0, SRIO = 0 and LLCS = 1. LLCIO pulled down => `Sleep Mode' is active, if I2C-bus bits FLDC = 0, SRIO = 1 and LLCS = 1. Table 4
SAA7140A; SAA7140B
To activate the scaler again, switch back to an active input clock, via SRIO and/or LLCS. In `Sleep Mode' the power consumption of the SAA7140A and SAA7140B is reduced to approximately 15% of its normal operational value.
VRAM port output data formats (VRO31 to VRO16) at FS2 bit = 0 and VOF bit = 1 (can be set via I2C-bus), burst mode only, Pixel order = n, n + 1, n + 2, etc. FS1 = 0; FS0 = 0 RGB (5, 5, 5) + 32-BIT WORDS(1)(2) n n+2 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+4 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 FS1 = 0; FS0 = 1 YUV 4 : 2 : 2 32-BIT WORDS(2)(3) n Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+2 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+4 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 FS1 = 1; FS0 = 0 YUV 4 : 2 : 2 16-BIT WORDS(2)(3) n Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+1 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 n+2 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 FS1 = 1; FS0 = 1 8-BIT MONOCHROME 32-BIT WORDS(4) n n+1 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n+4 n+5 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n+8 n+9 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0
PIXEL OUTPUT BITS VRO31 VRO30 VRO29 VRO28 VRO27 VRO26 VRO25 VRO24 VRO23 VRO22 VRO21 VRO20 VRO19 VRO18 VRO17 VRO16 Notes
R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
1. = keying bit. 2. RGB and YUV = digital signals. 3. e = even pixel numbers. 4. a and b = consecutive pixels.
1996 Sep 04
36
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
Table 5
SAA7140A; SAA7140B
VRAM port output data formats (VRO15 to VRO0) at FS2 bit = 0 and VOF bit = 1 (can be set via I2C-bus), burst mode only, Pixel order = n, 1n, 2n, etc. FS1 = 0; FS0 = 0 RGB (5, 5, 5) + 32-BIT WORDS(1)(2) n+1 n+3 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+5 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 FS1 = 0; FS0 = 1 YUV 4 : 2 : 2 32-BIT WORDS(2)(3)(4) n+1 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 n+3 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 n+5 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 FS1 = 1; FS0 = 0 YUV 4 : 2 : 2 16-BIT WORDS(2) OUTPUT NOT USED X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X FS1 = 1; FS0 = 1 8-BIT MONOCHROME 32-BIT WORDS(5) n+2 n+3 Yc7 Yc6 Yc5 Yc4 Yc3 Yc2 Yc1 Yc0 Yd7 Yd6 Yd5 Yd4 Yd3 Yd2 Yd1 Yd0 n+6 n+7 Yc7 Yc6 Yc5 Yc4 Yc3 Yc2 Yc1 Yc0 Yd7 Yd6 Yd5 Yd4 Yd3 Yd2 Yd1 Yd0 n + 10 n + 11 Yc7 Yc6 Yc5 Yc4 Yc3 Yc2 Yc1 Yc0 Yd7 Yd6 Yd5 Yd4 Yd3 Yd2 Yd1 Yd0
PIXEL OUTPUT BITS VRO15 VRO14 VRO13 VRO12 VRO11 VRO10 VRO9 VRO8 VRO7 VRO6 VRO5 VRO4 VRO3 VRO2 VRO1 VRO0 Notes
R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
1. = keying bit. 2. RGB and YUV = digital signals. 3. o = odd pixel numbers. 4. e = even pixel numbers. 5. c and d = consecutive pixels.
1996 Sep 04
37
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
Table 6
SAA7140A; SAA7140B
VRAM port output data formats (VRO31 to VRO16) at FS2 bit = 1 and VOF bit = 1 (can be set via I2C-bus), burst and transparent mode, Pixel order = n, n + 1, n + 2, etc. FS1 = 0; FS0 = 0 RGB (5, 5, 5) + 16-BIT WORDS(1)(2) n n+1 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+2 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 FS1 = 0; FS0 = 1 YUV 4 : 2 : 2 16-BIT WORDS(2)(3) n Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+1 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+2 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 FS1 = 1; FS0 = 0 RGB (8, 8, 8) 24-BIT WORDS(2) n R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 n+1 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 n+2 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 FS1 = 1; FS0 = 1 8-BIT MONOCHROME 16-BIT WORDS(4) n n+1 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n+2 n+3 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n+4 n+5 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0
PIXEL OUTPUT BITS VRO31 VRO30 VRO29 VRO28 VRO27 VRO26 VRO25 VRO24 VRO23 VRO22 VRO21 VRO20 VRO19 VRO18 VRO17 VRO16 Notes
R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
1. = keying bit. 2. RGB and YUV = digital signals. 3. e = even pixel numbers. 4. a and b = consecutive pixels.
1996 Sep 04
38
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
Table 7
SAA7140A; SAA7140B
VRAM port output data formats (VRO15 to VRO0) at FS2 bit = 1 and VOF bit = 1 (can be set via I2C-bus), burst and transparent mode, Pixel order = n, n + 1, n + 2, etc. FS1 = 0; FS0 = 0 RGB (5, 5, 5) + 16-BIT WORDS(1)(2) n n+1 X X X X X X X X () () () () () () () n+2 X X X X X X X X () () () () () () () FS1 = 0; FS0 = 1 YUV 4 : 2 : 2 16-BIT WORDS(1)(2) n X X X X X X X X () () () () () () () n+1 X X X X X X X X () () () () () () () n+2 X X X X X X X X () () () () () () () FS1 = 1; FS0 = 0 RGB (8, 8, 8) 24-BIT WORDS(1)(2) n B7 B6 B5 B4 B3 B2 B1 B0 () () () () () () () n+1 B7 B6 B5 B4 B3 B2 B1 B0 () () () () () () () n+2 B7 B6 B5 B4 B3 B2 B1 B0 () () () () () () () FS1 = 1; FS0 = 1 8-BIT MONOCHROME 16-BIT WORDS(1) n n+1 X X X X X X X X () () () () () () () n+2 n+3 X X X X X X X X () () () () () () () n+4 n+5 X X X X X X X X () () () () () () ()
PIXEL OUTPUT BITS VRO15 VRO140 VRO13 VRO12 VRO11 VRO10 VRO9 VRO8 VRO7 VRO6 VRO5 VRO4 VRO3 VRO2 VRO1 VRO0 Notes
X X X X X X X X () () () () () () ()
1. = keying bit. 2. RGB = digital signals.
1996 Sep 04
39
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
Table 8
SAA7140A; SAA7140B
Optional VRAM port output data formats (VRO31 to VRO16) at FS2 bit = 0 and VOF bit = 0 (can be set via I2C-bus), burst mode only; Pixel order = n, n + 1, n + 2, etc.; VMUX = 1 or 0 FS1 = 0, FS0 = 0 RGB (5, 5, 5) + 32-BIT LONG WORD(1)(2)(3) n 1 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z n+2 1 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z FS1 = 0, FS0 = 1 YUV 4 : 2 : 2 32-BIT LONG WORD(2)(4) n 1 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z n+2 1 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z FS1 = 1, FS0 = 1 8-BIT MONOCHROME 32-BIT LONG WORD(5) n n+1 1 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z n+4 n+5 1 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
PIXEL OUTPUT BITS
VRO31 VRO30 VRO29 VRO28 VRO27 VRO26 VRO25 VRO24 VRO23 VRO22 VRO21 VRO20 VRO19 VRO18 VRO17 VRO16 Notes
R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
1. = keying bit. 2. RGB and YUV = digital signals. 3. Z = high ohmic (3-state). 4. e = even pixel numbers. 5. a and b = consecutive pixels.
1996 Sep 04
40
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
Table 9
SAA7140A; SAA7140B
Optional VRAM port output data formats (VRO15 to VRO0) at FS2 bit = 0 and VOF bit = 0 (can be set via I2C-bus), burst mode only; Pixel order = n, n + 1, n + 2, etc.; VMUX = 1 or 0 FS1 = 0, FS0 = 0 RGB (5, 5, 5) + 32-BIT LONG WORD(1)(2)(3) n+1 1 0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 1 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z n+3 0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 1 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z FS1 = 0, FS0 = 1 YUV 4 : 2 : 2 32-BIT LONG WORD(2)(3)(4)(5) n+1 0 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 1 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z n+3 0 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 1 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z FS1 = 1, FS0 = 1 8-BIT MONOCHROME 32-BIT LONG WORD(3)(6) n+2 n+3 0 Yc7 Yc6 Yc5 Yc4 Yc3 Yc2 Yc1 Yc0 Yd7 Yd6 Yd5 Yd4 Yd3 Yd2 Yd1 Yd0 1 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z n+6 n+7 0 Yc7 Yc6 Yc5 Yc4 Yc3 Yc2 Yc1 Yc0 Yd7 Yd6 Yd5 Yd4 Yd3 Yd2 Yd1 Yd0
PIXEL OUTPUT BITS
VRO15 VRO14 VRO13 VRO12 VRO11 VRO10 VRO9 VRO8 VRO7 VRO6 VRO5 VRO4 VRO3 VRO2 VRO1 VRO0 Notes
Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
1. = keying bit. 2. RGB and YUV = digital signals. 3. Z = high ohmic (3-state). 4. o = odd pixel numbers. 5. e = even pixel number. 6. c and d = consecutive pixels.
1996 Sep 04
41
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
8 8.1 I2C-BUS PROTOCOL I2C-bus format
SAA7140A; SAA7140B
Table 10 I2C-bus format S SLAVE ADDRESS ACK SUBADDRESS ACK DATA0 ACK X DATAn ACK P
Table 11 Description of I2C-bus format CODE S Slave address ACK Subaddress Data P X START condition 0111 00X = IICSA = LOW or 0111 001X = IICSA = HIGH acknowledge generated by the slave subaddress byte (if more than 1 data byte is transmitted then an auto-increment of the subaddress is performed) data byte STOP condition read/write control bit: X = 0, order to write (the circuit is slave receiver) X = 1, order to read (the circuit is slave transmitter) Table 12 I2C-bus status byte (X in address byte = 1; 71H at IICSA = LOW or 73H at IICSA = HIGH) DATA BITS FUNCTION D7 Status byte (subaddress 20H) ID3 D6 ID2 D5 ID1 D4 ID0 D3 X D2 X D1 X D0 X DESCRIPTION
Table 13 Function of status bits ID3 to ID0 (software model of SAA7140A and SAA7140B compatible) ID3 0 ID2 0 ID1 0 ID0 0 VERSION V0 (first version)
Remark: With the exception of subaddress 20H (read only) all I2C-bus registers are read/write registers.
1996 Sep 04
42
8.2
I2C-bus bitmap
1996 Sep 04 DATA BITS D7 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B YSCI7 X X XSCI7 X XSCI6 X YSCI6 X CYB7 CYB6 DCGX2 CYA7 CYA6 FLIP YACM PFUV3 PFUV2 PFUV1 YACL5 CYA5 CYB5 DCGX1 XSCI5 X YSCI5 X CXUV7 CXUV6 CXUV5 CXY7 CXY6 CXY5 X XACM(4) XPSC5 XPSC4 CXY4 CXUV4 PFUV0 YACL4 CYA4 CYB4 DCGX0 XSCI4 X YSCI4 X X YP6(4) YP5 YP4 X YO10 YO9 YO8 X YP3 XPSC3 CXY3 CXUV3 PFY3 YACL3 CYA3 CYB3 X XSCI3 XSCI11 YSCI3 X YS7 YS6 YS5 YS4 YS3 YO7 YO6 YO5 YO4 YO3 XP7 XP6 XP5 XP4 XP3 XP2 YO2 YS2 YS10 YP2 XPSC2 CXY2 CXUV2 PFY2 YACL2 CYA2 CYB2 DCGY2 XSCI2 XSCI10 YSCI2 X X XO10 XO9 XO8 X XS10 XS7 XS6 XS5 XS4 XS3 XS2 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XS1 XS9 XP1 YO1 YS1 YS9 YP1 XPSC1 CXY1 CXUV1 PFY1 YACL1 CYA1 CYB1 DCGY1 XSCI1 XSCI9 YSCI1 YSCI9 X SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 X CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 SHVS YUV8 MCT RTB DIT FS2 FS1 FS0 BRIG0 CONT0 SATN0 XO0 XS0 XS8 XP0 YO0 YS0 YS8 YP0 XPSC0 CXY0 CXUV0 PFY0 YACL0 CYA0 CYB0 DCGY0 XSCI0 XSCI8 YSCI0 YSCI8 VSYP(4) REHAW REVAW VSI HSI VIPSI LLCS SRIO(4) FLDC VIDC VD1 VD0 HD1 HD0 PXQD LLCD VPE TTR(4) VOF QPP OF1 OF0 LW1 LW0 FSEL RSEN(4) SREGS IREGS INVOE REVFLD FICO1 FICO0 D6 D5 D4 D3 D2 D1 D0 DF(1)
Table 14 I2C-bus decoder control; subaddress and data bytes for writing (X in address byte = 0; 70H at IICSA = LOW or 72H at IICSA = HIGH); programming set A: subaddress = 02H to 1FH
FUNCTION SUBADDRESS
Philips Semiconductors
Initial settings expansion/DMSD
Initial settings VRAM
Expansion port output control
Expansion I/O control; scaler source control
Expansion/VRAM format control
Luminance brightness
Luminance contrast
High Performance Scaler (HPS)
Chroma saturation
Horizontal window
start(2)
Horizontal window length(2)
(continue)
43
Horizontal phase offset
Vertical window start(3)
Vertical window length(3)
(continue)
Vertical phase offset
Horizontal prescaling
Horizontal weighting control (select Y)
Horizontal weighting control (select UV)
Prefilter YUV
Vertical interpolation control
Vertical weighting control 1
Vertical weighting control 2
DC gain normalization
Horizontal scaling increment
(continue)
SAA7140A; SAA7140B
Vertical scaling increment
Objective specification
(continue)
DATA BITS D7 1C 1D 1E 1F UL7 UL6 UL5 UL4 UL3 UL2 UL1 UL0 UU7 UU6 UU5 UU4 UU3 UU2 UU1 UU0 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0 VU7 VU6 VU5 VU4 VU3 VU2 VU1 VU0 D6 D5 D4 D3 D2 D1 D0 DF(1)
FUNCTION SUBADDRESS
1996 Sep 04 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 XSCI7 X CYB7 CYA7 CYA6 CYB6 DCGX2 XSCI6 FLIP YACM PFUV3 PFUV2 CXUV7 CXUV6 CXY7 CXY6 CXY5 CXUV5 PFUV1 YACL5 CYA5 CYB5 DCGX1 XSCI5 X XACM(4) XPSC5 YPF YP6(4) YP5 X YO10 YO9 YO8 YP4 XPSC4 CXY4 CXUV4 PFUV0 YACL4 CYA4 CYB4 DCGX0 XSCI4 YS7 YS6 YS5 YS4 YO7 YO6 YO5 YO4 YO3 YS3 X YP3 XPSC3 CXY3 CXUV3 PFY3 YACL3 CYA3 CYB3 X XSCI3 XP7 XP6 XP5 XP4 XP3 X XO10 XO9 XO8 X XS7 XS6 XS5 XS4 XS3 XO7 XO6 XO5 XO4 XO3 XO2 XS2 XS10 XP2 YO2 YS2 YS10 YP2 XPSC2 CXY2 CXUV2 PFY2 YACL2 CYA2 CYB2 DCGY2 XSCI2 X SATN6 SATN5 SATN4 SATN3 SATN2 X CONT6 CONT5 CONT4 CONT3 CONT2 BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 CONT1 SATN1 XO1 XS1 XS9 XP1 YO1 YS1 YS9 YP1 XPSC1 CXY1 CXUV1 PFY1 YACL1 CYA1 CYB1 DCGY1 XSCI1 SHVS YUV8 MCT RTB DIT FS2 FS1 VSYP(4) REHAW REVAW VSI HSI VIPSI SRIO(4) FS0 BRIG0 CONT0 SATN0 XO0 XS0 XS8 XP0 YO0 YS0 YS8 YP0 XPSC0 CXY0 CXUV0 PFY0 YACL0 CYA0 CYB0 DCGY0 XSCI0 FLDC VIDC VD1 VD0 HD1 HD0 PXQD LLCD LLCS PEN3(4) PORT3 PORT2 PORT1 PORT0 PEN2(4) PEN1(4) PEN0(4) ID3 ID2 ID1 ID0 X X X X
Chroma keying upper limit for V
Chroma keying lower limit for V
Chroma keying upper limit for U
Philips Semiconductors
Chroma keying lower limit for U
Programming set B; subaddress = 22H to 3FH
Read only register
I/O port enable
Expansion port output control
Expansion I/O control; scaler source control
Expansion/VRAM format control
High Performance Scaler (HPS)
Luminance brightness
Luminance contrast
Chroma saturation
Horizontal window start(5)
44
Horizontal window
length(5)
(continue)
Horizontal phase offset
Vertical window
start(6)
Vertical window
length(6)
(continue)
Vertical phase offset
Horizontal prescaling
Horizontal weighting control (select Y)
Horizontal weighting control (select UV)
Prefilter YUV
Vertical interpolation control
Vertical weighting control 1
Vertical weighting control 2
DC gain normalization
SAA7140A; SAA7140B
Objective specification
Horizontal scaling increment
DATA BITS D7 39 3A 3B 3C 3D 3E 3F UL7 UL6 UL5 UL4 UL3 UL2 UL1 UL0 UU7 UU6 UU5 UU4 UU3 UU2 UU1 UU0 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0 VU7 VU6 VU5 VU4 VU3 VU2 VU1 VU0 X X X X X X YSCI9 YSCI8 YSCI7 YSCI6 YSCI5 YSCI4 YSCI3 YSCI2 YSCI1 YSCI0 X X X X XSCI11 XSCI10 XSCI9 XSCI8 D6 D5 D4 D3 D2 D1 D0 DF(1)
FUNCTION SUBADDRESS
1996 Sep 04
(continue)
Vertical scaling increment
(continue)
Philips Semiconductors
Chroma keying upper limit for V
Chroma keying lower limit for V
Chroma keying upper limit for U
Chroma keying lower limit for U
Notes
1. Default register contents to be filled in by hand.
2. Continued in 0A.
High Performance Scaler (HPS)
3. Continued in 0E.
4. Bits set to logic 1 after reset (all other bits set to logic 0 after reset).
5. Continued in 2A.
6. Continued in 2E.
45
SAA7140A; SAA7140B
Objective specification
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
8.3 Description of the I2C-bus bits
SAA7140A; SAA7140B
Tables 15 to 21 give the function of the register bits given in Table 14. 8.3.1 INITIAL SETTINGS FOR THE EXPANSION AND DMSD PORT; SUBADDRESS 00H
Table 15 Field detection; data bits FICO1 to FICO0 FICO1 0 0 1 1 FICO0 0 1 0 1 DESCRIPTION field sequence as detected from H and V sync signals field sequence synchronized to H and V but noise limited free running field sequence reserved
Table 16 Reference edge selection for the V sync input of the field detection; data bit REVFLD REVFLD 0 1 rising edge is reference falling edge is reference DESCRIPTION
Table 17 Polarity selection for the H sync input of the field detection (note 1); data bit INVOE INVOE 0 1 Note 1. INVOE may also be used for FDIO and FLDV output signal inversion Table 18 Polarity of I2C-bus register set ID; data bit IREGS IREGS 0 1 register set ID as defined by SREGS register set ID inverted DESCRIPTION DESCRIPTION active LOW, e.g. for SAA71xx signals similar to HREF active HIGH, e.g. for SAA71xx signals similar to HS
Table 19 Fix I2C-bus register set ID; data bit SREGS SREGS 0 1 DESCRIPTION register set ID toggles as detected and defined by FICO0 and FICO1 register set ID fixed to 1 (register set B selected)
Table 20 Enable of reference signals PXQIO, HIO, VIO, FDIO, LLCIO (expansion port) and PXQV, HGTV, VSYV, FLDV (VRAM port); data bit RSEN RSEN 0 1 reference signals enabled reference signals disabled DESCRIPTION
1996 Sep 04
46
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
Table 21 Field sync definition; data bit FSEL FSEL 0 1 8.3.2 DESCRIPTION V input for field detection to be handled as V sync signal
SAA7140A; SAA7140B
V input for field detection to be handled as frame sync signal
INITIAL SETTINGS FOR THE VRAM PORT; SUBADDRESS 01H
Table 22 First pixel position in VRO data for FS1 = 0; FS0 = 0 (RGB) and FS1 = 0; FS0 = 1 (YUV); data bits LW1 and LW0 LW1 0 0 1 1 LW0 0 1 0 1 BITS 31 to 24 pixel 0 pixel 0 black black BITS 23 to 16 pixel 0 pixel 0 black black BITS 15 to 8 pixel 1 pixel 1 pixel 0 pixel 0 BITS 7 to 0 pixel 1 pixel 1 pixel 0 pixel 0 FS2 = 0; TTR = 0 REMARK
Table 23 First pixel position in VRO data for FS1 = 1; FS0 = 1 (monochrome) LW1 0 0 1 1 0 0 1 1 LW0 0 1 0 1 0 1 0 1 BITS 31 to 24 pixel 0 black black black pixel 0 black pixel 0 black BITS 23 to 16 pixel 1 pixel 0 black black pixel 1 pixel 0 pixel 1 pixel 0 BITS 15 to 8 pixel 2 pixel 1 pixel 0 black X X X X BITS 7 to 0 pixel 3 pixel 2 pixel 1 pixel 0 X X X X FS2 = 1; TTR = 0; LW only affects the grey scale format FS2 = 0; TTR = 0 REMARK
Table 24 Set output field mode; data bits OF1 to OF0 OF1 0 0 1 1 OF0 0 1 0 1 DESCRIPTION both fields for interlaced storage both fields for non-interlaced storage odd fields only (even fields ignored) for non-interlaced storage even fields only (odd fields ignored) for non-interlaced storage
Table 25 Pixel qualifier polarity flag; data bit QPP QPP 0 1 PXQV is active LOW (pin 41) PXQV is active HIGH DESCRIPTION
Table 26 VRAM-port output format; data bit VOF VOF 0 1 DESCRIPTION enabling of 32 to 16-bit multiplexing via VMUX disabling of 32 to 16-bit multiplexing via VMUX
1996 Sep 04
47
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
Table 27 VRAM-port mode selection; data bit TTR TTR 0 1 FIFO mode (VRAM data burst transfer) transparent mode DESCRIPTION
SAA7140A; SAA7140B
Table 28 VRAM-port outputs enable; data bit VPE VPE 0 1 8.3.3 DESCRIPTION HFL and INCADR inactive (HFL = LOW, INCADR = HIGH); VRO outputs in 3-state HFL and INCADR enabled; VRO outputs dependent on VOEN
PORT I/O CONTROL; SUBADDRESS 21H
Table 29 Select direction of PORT3 to PORT0; data bits PEN3 to PEN0 PEN3 TO PEN0 PENx = 0 PENx = 1 PORTx set to output PORTx set to input DESCRIPTION
Table 30 Status of port I/O's, pins 32 (PORT3) to 35 (PORT0) PORT3 to PORT0 Write mode Read mode DESCRIPTION set status of PORT3 to PORT0 registers (applied to pins 32 to 35 if PENx = 0) read status of PORT3 to PORT0; if PENx = 0 then status of PORTx register; if PENx = 1 then status of external driven data
8.3.4
REGISTER SET A (02H TO 1FH) AND B (22H TO 3FH)
Table 31 Source select for expansion port clock output LLCIO (note 1 ); data bit LLCD LLCD 0 1 Note 1. The clock output on LLCIO may be disabled by I2C-bus bits SRIO = 1 and LLCS = 1; see Table 37. Table 32 Source select for expansion port pixel qualifier and data output at PXQIO and VIDH/VIDL[7 to 0] (note 1); data bit PXQD PXQD 0 1 Note 1. The qualifier output on PXQIO may be disabled by I2C-bus bits SRIO = 1 and VIPSI = 1; see Table 38. DESCRIPTION sources are corresponding signals from DMSD port sources are corresponding signals from scaler output source is clock from DMSD port source is clock input from expansion port, as defined by SRIO DESCRIPTION
1996 Sep 04
48
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
Table 33 Source select for expansion port horizontal sync output HIO (note 1); data bits HD1 to HD0 HD1 0 0 1 1 Note 1. If SRIO and HSI = 1 then HIO output is disabled. HD0 0 1 0 1 DESCRIPTION source is corresponding signal from DMSD port source is HIN from expansion port (short-cut) source is corresponding signal from scaler output source is HIN from expansion port
Table 34 Source select for expansion port vertical sync output VIO (note 1); data bits VD1 to VD0 VD1 0 0 1 1 Note 1. If SRIO and VSI = 1 then VIO output is disabled. VD0 0 1 0 1 DESCRIPTION source is corresponding signal from DMSD port source is VIN from expansion port (short-cut) source is corresponding signal from scaler output source is VIN from expansion port
Table 35 I/O control for the expansion port data output VIDH7 to VIDH0 and VIDL7 to VIDL0 (dependent on YUV8 programming for FLDC = 0) (note 1); data bit VIDC YUV8 0 0 1 1 Note 1. If FLDC and FDIO) = 1 the outputs VIDH/VIDL are disabled. Table 36 FDIO I/O control and signal definition; data bit FLDC FLDC 0 1 - - FDIO - - 0 1 DESCRIPTION FDIO contains odd/even flag FLD and is switched to output FDIO may be provided with a 7196 DIR like signal and is switched to input LLCIO, PXQIO and VIDH/VIDL I/O definition as defined by the I2C-bus parameters selected outputs are forced to input mode and corresponding signals are used as scaler input VIDC 0 1 0 1 VIDH = output, VIDL = output VIDH = input, VIDL = input VIDH = output, VIDL = input VIDH = input, VIDL = output DESCRIPTION
1996 Sep 04
49
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
Table 37 Source select for scaler clock input; data bit LLCS (03H to 23H) FLDC X X 0 1 1 FDIO X X X 0 1 SRIO X 0 1 1 1 LLCS 0 1 1 1 1
SAA7140A; SAA7140B
DESCRIPTION source is LLC from DMSD port source is LLCIN from expansion port source is LLCIO input from expansion port, output is disabled source is derived from LLCIO output; LLCD = 0 from LLC of decoder port, LLCD = 1 not allowed source is LLCIO input from expansion port, output is disabled
Table 38 Source select for scaler data and pixel qualifier input; data bit VIPSI FLDC 0 0 FDIO X X SRIO X - VIPSI 0 1 DESCRIPTION source is data and CREF from DMSD port source is data input VIDH/VIDL: when the pixel qualifier is PXQIN from expansion port FLDC = 0, FDIO = x, SRIO = 0 and VIPSI = 1; when the pixel qualifier is PXQIO from expansion port, output disabled FLDC = 0, FDIO = x, SRIO = 1 and VIPSI = 1; source is derived from data output VIDH/VIDL, from decoder port for PXQD = 0, PXQD = 1 is not allowed: when the pixel qualifier is PXQIN from expansion port FLDC = 1, FDIO = 0, SRIO = 0 and VIPSI = x; when the pixel qualifier is CREF via the PXQIO output for PXQD = 0, PXQD = 1 is not allowed FLDC = 1, FDIO = 0, SRIO = 1 and VIPSI = x source is data input VIDH/VIDL, output disabled, when the pixel qualifier is PXQIN from expansion port FLDC = 1, FDIO = 1, SRIO = 0 and VIPSI = x; when the pixel qualifier is PXQIO from expansion, port output disabled FLDC = 1, FDIO = 1, SRIO = 1 and VIPSI = x
1
0
-
X
1
1
-
X
Table 39 Source select for scaler horizontal sync input; data bit HSI SRIO X 0 1 HSI 0 1 1 source is HREF from DMSD port source is HIN from expansion port source is HIO from expansion port, HIO output disabled DESCRIPTION
Table 40 Source select for scaler vertical sync input and field detection H/V; data bit VSI SRIO X 0 1 VSI 0 1 1 DESCRIPTION source is VS from DMSD port; VS and HREF for field detection source is VIN from expansion port; VIN and HIN for field detection source is VIO from expansion port; VIO and HIO for field detection
Table 41 Reference edge selection for the V sync input of the acquisition window; data bit REVAW REVAW 0 1 rising edge is reference falling edge is reference DESCRIPTION
1996 Sep 04
50
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
Table 42 Reference edge selection for the H-sync input of the acquisition window; data bit REHAW REHAW 0 1 rising edge is reference falling edge is reference DESCRIPTION
Table 43 Expansion-port clock and reference signal selection; data bit SRIO (see Tables 37 to 40) SRIO 0 1 DESCRIPTION clock and reference signals are taken from xxxIN pins clock and reference signals are taken from xxxIO pin, xxxIN pins are ignored
Table 44 VSYV output signal polarity; data bit VSYP VSYP 0 1 VSYV contains 1 active V sync signals VSYV contains 0 active V sync signals DESCRIPTION
Table 45 VRAM port output format select; data bits FS2 to FS0 (04H to 24H); see Tables 6 and 7 FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 OUTPUT FORMAT RGB (5, 5, 5) + ; 2 x 16-bit/pixel; 32-bit word length; RGB matrix on, VRAM output format YUV 4 : 2 : 2; 2 x 16-bit/pixel; 32-bit word length; RGB matrix off, VRAM output format YUV 4 : 2 : 2; 1 x 16-bit/pixel; 16-bit word length; RGB matrix off, optional output format monochrome mode; 4 x 8-bit/pixel; 32-bit word length; RGB matrix off, VRAM output format RGB (5, 5, 5) + ; 1 x 16-bit/pixel; 16-bit word length; RGB matrix on, VRAM output + transparent format YUV 4 : 2 : 2 + ; 1 x 16-bit/pixel; 16-bit word length; RGB matrix off; VRAM output + transparent format RGB (8, 8, 8) + ; 1 x 24-bit/pixel; 24-bit word length; RGB matrix on, VRAM output + transparent format monochrome mode; 2 x 8-bit/pixel; 16-bit word length; RGB matrix off, VRAM output + transparent format
Table 46 Dithering (noise shaping) control (for VRAM port only); data bit DIT DIT 0 1 dithering on dithering off DESCRIPTION
Table 47 ROM table for anti-gamma correction (for VRAM port only); data bit RTB RTB 0 1 1996 Sep 04 ROM table switched on ROM table switched off 51 DESCRIPTION
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
Table 48 Monochrome and two's complement output data select; data bit MCT MCT 0 1 DESCRIPTION
SAA7140A; SAA7140B
inverse grey scale luminance (if grey scale is selected by FS bits) or straight binary U, V data output non-inverse monochrome luminance (if grey scale is selected by FS bits) or two's complement U, V data output
Table 49 Expansion port data path configuration; data bit YUV8; see Tables 8 and 9 YUV8 0 1 expansion port set to 16-bit YUV expansion port set to 8-bit YUV (VIDL7 to VIDL0) DESCRIPTION
Table 50 Select field sequence, H and V; data bit SHVS SHVS 0 1 use separate H and V input signals use decoded information from the CCIR 656 data stream (only for YUV8 = 1) DESCRIPTION
Table 51 Luminance brightness control; data bits BRIG7 to BRIG0 (05H to 25H) D7 1 ... 1 ... 0 D6 1 ... 0 ... 0 D5 1 ... 0 ... 0 D4 1 ... 0 ... 0 D3 1 ... 0 ... 0 D2 1 ... 0 ... 0 D1 1 ... 0 ... 0 D0 1 ... 0 ... 0 GAIN 255 (bright) .... 128 (CCIR level) .... 0 (dark)
Table 52 Luminance contrast control; data bits CONT6 to CONT0 (06H to 26H) D7 0 ... 0 ... 0 D6 1 ... 1 ... 0 D5 1 ... 0 ... 0 D4 1 ... 0 ... 0 D3 1 ... 0 ... 0 D2 1 ... 0 ... 0 D1 1 ... 0 ... 0 D0 1 ... 0 ... 0 GAIN 1.999 (maximum contrast) .... 1 (CCIR level) .... 0 (luminance off)
Table 53 Chrominance saturation control; data bits SATN6 to SATN0 (07H to 27H) D7 0 ... 0 ... 0 D6 1 ... 1 ... 0 D5 1 ... 0 ... 0 D4 1 ... 0 ... 0 D3 1 ... 0 ... 0 D2 1 ... 0 ... 0 D1 1 ... 0 ... 0 D0 1 ... 0 ... 0 GAIN 1.999 (maximum contrast) .... 1 (CCIR level) .... 0 (colour off)
1996 Sep 04
52
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
Table 54 X (horizontal) offset definition, counted in input pixel qualifiers; data bits XO10 to XO0 XO10 to XO0 08H to 28H and 0AH to 2AH DESCRIPTION Defines the start position of the X processing window
Table 55 X (horizontal) source size definition, counted in input pixel qualifiers; data bits XS10 to XS0 XS10 to XS0 09H to 29H and 0AH to 2AH DESCRIPTION defines the length of the X processing window
Table 56 Start phase for horizontal variable phase scaling (defined by XSCI11 to XSCI0); data bits XP6 to XP0 XP6 to XP0 0BH to 2BH DESCRIPTION XPSTART = XP/128 x TPXQ (TPXQ = distance between 2 pixels)
Table 57 X phase value fixed; data bit XP7 XP7 0 1 DESCRIPTION sample phase is calculated for every qualified sample sample phase is fixed to the value set by XP6 to XP0
Table 58 Y (vertical) offset definition, counted in input horizontal sync events; YO10 to YO0 YO10 to YO0 0CH to 2CH and 0EH to 2EH DESCRIPTION defines the start position of the Y processing window
Table 59 Y (vertical) source size definition, counted in input horizontal sync events; YS10 to YS0 YS10 to YS0 0DH to 2DH and 0EH to 2EH DESCRIPTION defines the length of the Y processing window
Table 60 Start phase for vertical scaling (defined by YSCI9 to YSCI0); data bits YP6 to YP0 YP6 to YP0 0FH to 2FH DESCRIPTION YPSTART = YP/128 x TLINE (TLINE = distance between 2 lines)
Table 61 Prescaling factor of the X prescaler; data bits XPSC5 to XPSC0 XPSC5 to XPSC0 10H to 30H DESCRIPTION defines accumulation sequence length and subsampling factor of the input data stream where NOP (XPSC) = TRUNC [NIN (XPSC + 1)] NOP = number of prescaler output pixel and NIN = number of qualified scaler input pixel
1996 Sep 04
53
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
Table 62 X (horizontal) prescaler accumulation mode of accumulating FIR; data bit XACM XACM 0 1 accumulating operates overlapping non overlapping accumulation (must be set to bypass the prescaler) DESCRIPTION
Table 63 Coefficient select for X prescaler (luminance component Y); data bits CXY7 to CXY0 CXY7 to CXY0 11H to 31H DESCRIPTION for DC gain compensation of prescaler the accumulated pixels can be weighted by 1 or 2. CXYi defines a sequence of 8 bits, which control the coefficients; when CXYi = 0 pixel weighted by 1 and when CXYi = 1 pixel weighted by 2
Table 64 Coefficient select for X prescaler (colour difference signals UV); data bits CXUV7 to CXUV0 CXUV7 to CXUV0 12H to 32H DESCRIPTION for DC gain compensation of prescaler the accumulated pixels can be weighted by 1 or 2. CXUVi defines a sequence of 8 bits, which control the coefficients; when CXUVi = 0 pixel weighted by 1 and when CXUVi = 1 pixel weighted by 2
Table 65 Prefilter selection for luminance component Y (note 1); data bits PFY3 to PFY0 (13H to 33H) PFY1 0 0 1 1 Note 1. H(z) = H1(z) x H2(z) x H3(z) with H1 and H3 = 1 + z-1; H2 = 1 + A x z-1 + z-2 and A = 2, 1516, 78, 34 for PFY3 and PFY2 = 00, 01, 10, 11. Table 66 Prefilter selection for colour difference signals UV (note 1); data bits PFUV3 to PFUV0 PFUV1 0 0 1 1 Note 1. H(z) = H1(z) x H2(z) x H3(z) with H1 = 1 + z-1; H2 = 1 + A x z-1 + z-2; H3 = 1 + z-2 and A = 2, 1516, 78, 34 for PFUV3 and PFUV2 = 00, 01, 10, 11. Table 67 Accumulation sequence length of the Y (vertical) processing; data bits YACL5 to YACL0 YACL5 to YACL0 14H to 34H DESCRIPTION defines vertical accumulation sequence length of input lines. If accumulation FIR filter mode is selected (YACM), YACL has to fit to the vertical scaling factor (defined by YSCI9 to YSCI0) PFUV0 0 1 0 1 H1(z) bypass active active active H2(z) bypass bypass active active H3(z) bypass bypass bypass active PFY0 0 1 0 1 H1(z) bypass active active active H2(z) bypass bypass bypass active H3(z) bypass bypass active active
1996 Sep 04
54
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
Table 68 Y (vertical) scaler accumulation (respectively calculation) mode of vertical arithmetic; data bit YACM YACM 0 1 DESCRIPTION arithmetic operates as a linear phase interpolator (LPI) arithmetic operates as accumulating FIR filter in vertical direction
Table 69 Horizontal flip `mirroring'; maximum pixels after prescaling = 384; data bit FLIP FLIP 0 1 output lines correspond to input lines output lines correspond flipped input lines (see Section 7.4.2) DESCRIPTION
Table 70 Coefficient select for Y (vertical) processing in accumulation mode (notes 1 and 2); data bits CYA7 to CYA0 and CYB7 to CYB0 (15H to 35H and 16H to 36H) CYBi 0 0 1 1 Notes 1. For improvement of vertical filtering the accumulated lines can be weighted. Weighting factor = 2(2 x CYBi + CYAi - 1) 2. The resulting factor as a function of a bit pattern CYAi, CYBi and the DC gain control DCGY, is given in Tables 71 and 72. Table 71 DC gain control of vertical scaler (see Table 2) (notes 1, 2 and 3) ; data bits DCGY2 to DCGY0 (17H to 37H) DCGY2 0 0 ... ... 1 Notes 1. Dependent on active coefficients and the sequence length, the amplitude gain has to be renormalized. 2. Gain factor = 2(DCGY + 1). 3. The resulting factor is a function of CYi and DCGY; 0 for (CYAi = CYBi = 0) or (CYAi = CYBi = 1 and DCGY = 0) or (DGCY > 5). The weighting/gain factor is given in Table 72. Table 72 Weighting factor as a function of gain factor CYI 0 1 2 3 DCGY0 0
1 2
CYAi 0 1 0 1
CYi 0 1 2 3
WEIGHTING FACTOR 0 1 2 4
DCGY1 0 0 .... .... 1
DCGY0 0 1 .... .... 1
DCGY 0 1 .... .... 7
GAIN FACTOR 2 4 .... .... 256
DCGY1 0
1 1 4 2
DCGY2 0
1 1 1 8 4 2
DCGY3 0
1 16 1 8 1 4
DCGY4 0
1 32 1 16 1 8
DCGY5 0
1 1 1 64 32 16
DCGY6 0 0 0 0
DCGY7 0 0 0 0
1 0
1
1996 Sep 04
55
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
Table 73 DC gain control of horizontal prescaler (see Table 1; note 1); data bits DCGX2 to DCGX0 DCGX2 0 0 0 0 1 1 1 1 Note 1. Dependent on the number of active coefficients `2' in the accumulation sequence and the sequence length, the output amplitude gain has to be renormalization via DCGX. Table 74 X scaler increment for variable phase scaling in horizontal pixel phase arithmetic (note 1); data bits XSCI11 to XSCI0 (18H to 38H and 19H to 39H) XSCI11 TO XSCI0 18H to 38H and 19H to 39H Note 1. Where NIP = number of qualified scaler input pixel and NOP = number of output pixel. Table 75 Y scaler increment for vertical down scaling; data bits YSCI9 to YSCI0 (1Ah to 3Ah and 1BH to 3BH) YSCI9 TO YSCI0 1AH to 3AH DESCRIPTION N IL YSCI = INT 1024 x ---------- - 1 ; for YACM = 0 = LPI mode N OL N OL YSCI = INT 1024 x 1 - ---------- ; for YACM = 1 = accumulation mode N IL N IP 1024 XSCI = INT ---------- x --------------------------------N OP ( XPSC + 1 ) DESCRIPTION DCGX1 0 0 1 1 0 0 1 1 DCGX0 0 1 0 1 0 1 0 1 GAIN x1 x 12 x 14 x 18 x 12 x 14 x 18 x 116
1BH to 3BH
Table 76 Set upper limit V for colour keying (8-bit; two's complement); data bits VU7 to VU0 (1CH to 3CH) VU7 1 0 0 VU6 0 0 1 VU5 0 0 1 VU4 0 0 1 VU3 0 0 1 VU2 0 0 1 VU1 0 0 1 VU0 0 0 1 limit = 0 as maximum positive value = +127 signal level DESCRIPTION as maximum negative value = -128 signal level
Table 77 Set lower limit V for colour keying (8-bit; two's complement); data bits VL7 to VL0 (1DH to 3DH) VL7 1 0 0 VL6 0 0 1 VL5 0 0 1 VL4 0 0 1 VL3 0 0 1 VL2 0 0 1 VL1 0 0 1 56 VL0 0 0 1 limit = 0 as maximum positive value = +127 signal level DESCRIPTION as maximum negative value = -128 signal level
1996 Sep 04
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
Table 78 Set upper limit U for colour keying (8-bit; two's complement); data bits UU7 to UU0 (1EH to 3EH) UU7 1 0 0 UU6 0 0 1 UU5 0 0 1 UU4 0 0 1 UU3 0 0 1 UU2 0 0 1 UU1 0 0 1 UU0 0 0 1 limit = 0 as maximum positive value = +127 signal level DESCRIPTION as maximum negative value = -128 signal level
Table 79 Set lower limit U for colour keying (8-bit; two's complement); data bits UL7 to UL0 (1FH to 3FH) UL7 1 0 0 UL6 0 0 1 UL5 0 0 1 UL4 0 0 1 UL3 0 0 1 UL2 0 0 1 UL1 0 0 1 UL0 0 0 1 limit = 0 as maximum positive value = +127 signal level DESCRIPTION as maximum negative value = -128 signal level
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD(bord) VDDD(core) VDDD VI VO Ptot Tstg Tamb Vesd Note 1. Pin 31 (SDA): 800 V. 10 HANDLING Inputs and output are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. 11 THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 60 UNIT K/W PARAMETER digital supply voltage for I/O section digital supply voltage for internal core digital supply voltage DC input voltage DC output voltage total power dissipation storage temperature operating ambient temperature electrostatic protection CONDITIONS SAA7140A SAA7140A SAA7140B SAA7140B SAA7140B SAA7140A SAA7140B MIN. -0.5 -0.5 -0.5 -0.5 -0.5 - - -65 0 2000(1) MAX. +6.5 +6.0 +6.0 V V V UNIT
VDDD + 0.5 V VDDD + 0.5 V 750 750 +150 70 - mW mW C C V
1996 Sep 04
57
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
12 DC CHARACTERISTICS
SAA7140A; SAA7140B
VDDD(bord) = 4.5 to 5.5 V; VDDD(core) = 3.0 to 3.6 V; VDDD = 3.0 to 3.6 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies; SAA7140A VDDD(bord) VDDD(core) IDDD(bord) IDDD(core) IDDD(tot) VDDD IDDD digital supply voltage for I/O section digital supply voltage for internal core digital supply current for I/O section digital supply current for internal core total digital supply current normal operation sleep mode normal operation sleep mode 4.5 3.0 - - - - - 5.0 3.3 30 10 60 10 100 5.5 3.6 - - - - - V V mA mA mA mA mA
Supplies; SAA7140B digital supply voltage digital supply current normal operation sleep mode Data, clock and control inputs VIL VIH VIL VIH ILI CI LOW level input voltage HIGH level input voltage LOW level input voltage HIGH level input voltage input leakage current input capacitance clocks clocks other inputs; SAA7140A other inputs; SAA7140B other inputs; SAA7140A other inputs; SAA7140B VIL = 0 V data clocks 3-state I/O; high-impedance state Data, clock and control outputs (note 1) VOL VOH VOH VOL LOW level output voltage HIGH level output voltage HIGH level output voltage LOW level output voltage all outputs; SAA7140A clocks; SAA7140B clocks; SAA7140A clocks; SAA7140B other outputs; SAA7140A other outputs; SAA7140B other outputs; SAA7140B 0 0 2.6 0.85VDDD 2.4 0.85VDDD 0 - - - - - - - 0.6 0.4 VDDD VDDD VDDD VDDD 0.4 V V V V V V V -0.5 2.4 -0.5 -0.5 2.0 2.4 - - - - - - - - - - - - - - 0.6 0.8 0.2VDDD V V V VDDD + 0.5 V 3.0 - - 3.3 90 10 3.6 - - V mA mA
VDDD + 0.5 V VDDD + 0.5 V 1 8 8 8 mA pF pF pF
1996 Sep 04
58
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2C-bus, SDA and SCL (pins 31 and 32) VIL LOW level input voltage SAA7140A SAA7140B VIH I31, 32 IACK Vo Note 1. Levels measured with load circuit; 1.2 k at 3 V (TTL load); CL = 40 pF. 13 AC CHARACTERISTICS VDDD(bord) = 4.5 to 5.5 V; VDDD(core) = 3.0 to 3.6 V; VDDD = 3.0 to 3.6 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - 50 - - - - - - - - - - - - - 49 - - TYP. MAX. UNIT HIGH level input voltage input current output current on pin 31 acknowledge output voltage at acknowledge I31 = 3 mA -0.5 -0.5 0.7VDDD - 3 - - - - - - - +1.5 0.3VDDD 10 - 0.4 V V A mA V
VDDD + 0.5 V
Clock input timing (LLC, LLCIN and LLCIO as input) (see Fig.20) tLLC, tLLCIN tr tf tVCLK tpL tpH tr tf tSU tHD tSU tHD CL tLLCIO tr tf cycle time duty factor rise time fall time tLLCH or tLLC 31 40 - - 45 60 5 6 ns % ns ns
VCLK input timing (for `Burst Mode' only, TTR = 0); note 1 (see Fig.19) VRAM port clock cycle time VCLK LOW time VCLK HIGH time rise time fall time note 2 note 3 note 3 0.6 V to 0.85VDDD 0.85VDDD to 0.6 V 30 12 12 - - 200 - - 5 6 - - - - ns ns ns ns ns
Data and control input timing, related to the corresponding input clock; (see Fig.20) set-up time hold time 11 3 ns ns
Data and control input timing at the expansion port, related to LLCIO output set-up time hold time 15 0 ns ns
Clock output timing (LLCIO and VCLK output); note 4 (see Fig.20) output load capacitance cycle time duty factor rise time fall time tLLCIOH or tLLCIO 0.6 V to 0.85VDDD 0.85VDDD to 0.6 V 15 31 38 - - 40 45 59 5 6 pF ns % ns ns
1996 Sep 04
59
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - -
TYP.
MAX.
UNIT
Data and control output timing at the expansion port, related to LLCIO output; (see Fig.20) CL tOHD tPD load capacitance output hold time propagation delay from positive edge of LLCIO output CL = 7.5 pF CL = 15 pF CL = 40 pF 15 1.5 - - 40 - - 15 pF ns ns ns
VRO and reference signal output timing, related to VCLK output; (see Fig.19) CL tOHD tOHL tOHV tOD output load capacitance VRO data hold time related to LCC scaler (INCADR, HFL) related to VCLK (HFL) VRO data delay time in burst mode (TTR = 0) VRO data delay time in transparent mode (TTR = 1) tODL tODV tD tE tHFL VOE tHFL VCLK Notes 1. LLCScaler may be LLC from DMSD port or LLCIN from expansion-port, dependent on scaler source clock selection via I2C-bus bit LLCS. 2. Maximum TVCLK = 200 ns for test mode only. The applicable maximum cycle time depends on data format, horizontal scaling and input data rate. 3. Measured at 1.5 V level; tpL may be infinite. 4. LLCIOout timing also valid for VCLKout in transparent mode; (see Fig.20). 5. Timings of VRO refer to the rising edge of VCLK. 6. The timing of INCADR and the rising edge of HFL always refers to LLCScaler. During a VRAM transfer, the falling edge of HFL is generated by VCLK. During horizontal increment and vertical reset cycles, both edges of HFL always refer to LLC scaler. 7. Asynchronous signals. Its timing refers to the 1.5 V switching point of VOEN input signal (pin 53). 8. The timing refers to the 1.5 V switching point of VMUX signal (pin 46) in 32 to 16-bit multiplexing mode. Corresponding pairs of VRO outputs are together connected. related to LCCScaler (INCADR,HFL) related to VCLK (HFL) VRO disable time to 3-state VRO enable time from 3-state HFL rising edge to VRAM port enable VRO outputs other outputs CL = 10 pF; note 5 CL = 10 pF; notes 6 and 1 CL = 10 pF; note 6 CL = 40 pF; note 5 CL = 40 pF; note 5 CL = 25 pF; notes 6 and 7 CL = 25 pF; note 6 CL = 40 pF; note 7 CL = 25 pF; note 8 CL = 40 pF; note 7 CL = 25 pF; note 8 no zooming 15 7.5 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - 40 25 - - - 25 15 60 60 40 24 40 25 810 840 pF pF ns ns ns ns ns ns ns ns ns ns ns ns ns
HFL rising edge to VCLK burst no zooming
1996 Sep 04
60
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
handbook, full pagewidth
2.4 V 1.5 V 0.6 V TVCLK tf tr 2.4 V
VOEN
VCLK
1.5 V 0.6 V tCH todVRO tohVRO 0.85VDD 0.4 V tod toh 0.85VDD tCL todVRO
tenVRO not valid DATA OUTPUT VRAM port
OUTPUT HFL
MHA125
0.4 V
Fig.19 Data output timing (VRAM port).
1996 Sep 04
61
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
handbook, full pagewidth
TLLC, TLLCIN tLLCH, tLLCINH 2.4 V
CLOCK INPUT LLC, LLCIN
1.5 V 0.6 V ts th tf tr
DATA AND CONTROL INPUTS (DMSD/EXPANSION PORT)
2.4 V not valid 0.6 V ts th 2.4 V
INPUT CREF, PXQIN (PXQIO if used as input) tod toh DATA AND CONTROL OUTPUTS EXPANSION PORT
0.6 V
0.85VDD 0.4 V
tLLCIOH
tLLCIOL 0.85VDD
CLOCK OUTPUT LLCIO
1.5 V 0.4 V tf tr
MHA124
Fig.20 Data input/output timing (DMSD port and expansion port).
1996 Sep 04
62
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
14 PACKAGE OUTLINE
SAA7140A; SAA7140B
LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm
SOT425-1
c
y X
A 102 103 65 64 ZE
e Q E HE A A2 A 1 (A 3) Lp pin 1 index 128 1 wM D HD ZD B vM B 39 38 bp vM A bp detail X L
wM
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT425-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 Q 0.70 0.58 v 0.2 w 0.12 y 0.1 Z D(1) Z E(1) 0.81 0.59 0.81 0.59 7 0o
o
22.15 16.15 21.85 15.85
ISSUE DATE 96-04-02
1996 Sep 04
63
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
15 SOLDERING 15.1 Introduction
SAA7140A; SAA7140B
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). 15.3.2 SO
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 15.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP and SO packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Manual" (order code 9398 510 63011). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 15.3 15.3.1 Wave soldering QFP
Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. 15.3.3 METHOD (QFP AND SO)
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Repairing soldered joints
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Sep 04
64
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7140A; SAA7140B
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Sep 04
65
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
NOTES
SAA7140A; SAA7140B
1996 Sep 04
66
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
NOTES
SAA7140A; SAA7140B
1996 Sep 04
67
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA51
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
657021/1200/02/pp68
Date of release: 1996 Sep 04
Document order number:
9397 750 01068

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